BIT LINE SENSE AMPLIFIER LAYOUT ARRAY, LAYOUT METHOD, AND APPARATUS HAVING THE SAME
    1.
    发明申请
    BIT LINE SENSE AMPLIFIER LAYOUT ARRAY, LAYOUT METHOD, AND APPARATUS HAVING THE SAME 有权
    位线检测放大器布局阵列,布局方法和具有相同功能的设备

    公开(公告)号:US20120044734A1

    公开(公告)日:2012-02-23

    申请号:US13213508

    申请日:2011-08-19

    IPC分类号: G11C5/06 H05K13/00

    CPC分类号: G11C7/065 G11C7/12 G11C7/18

    摘要: A bit line sense amplifier layout array includes N sense amplifier layout regions, which are arranged adjacent each other and have a sense amplifier, respectively. (N+1−i) bit lines and i complementary bit lines are arranged in an ith sense amplifier layout region among the sense amplifier layout regions. An ith bit line among the (N+1−i) bit lines and an ith complementary bit line among the i complementary bit lines are connected to a sense amplifier formed in the ith sense amplifier layout region. The values N and i are natural numbers and i>=1 and

    摘要翻译: 位线读出放大器布局阵列包括N个读出放大器布局区域,它们彼此相邻布置并分别具有读出放大器。 (N + 1-i)位线和i个互补位线被布置在读出放大器布局区域中的第i个读出放大器布局区域中。 (N + 1-i)位线中的第i位线和i互补位线之间的第i个互补位线连接到形成在第i个读出放大器布局区域中的读出放大器。 值N和i是自然数,i> = 1和<= N。