公开(公告)号：US20140191231A1

公开(公告)日：2014-07-10

申请号：US14206858

申请日：2014-03-12

Applicant: JAPAN DISPLAY INC.

Inventor： Tetsuya SHIBATA ,  Hajime Watakabe ,  Atsushi Sasaki ,  Yuki Matsuura ,  Muneharu Akiyoshi ,  Hiroyuki Watanabe

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: According to one embodiment, a method of manufacturing a thin-film transistor circuit substrate including forming an oxide semiconductor thin film above an insulative substrate, forming a gate insulation film and a gate electrode which are stacked on a first region of the oxide semiconductor thin film, and exposing from the gate insulation film a second region and a third region of the oxide semiconductor thin film, the second region and the third region being located on both sides of the first region of the oxide semiconductor thin film, forming an interlayer insulation film of silicon nitride including dangling bonds of silicon, the interlayer insulation film covering the second region and the third region of the oxide semiconductor thin film, the gate insulation film and the gate electrode, and forming a source electrode and a drain electrode.

Abstract translation: 根据一个实施例，制造薄膜晶体管电路衬底的方法包括在绝缘衬底上形成氧化物半导体薄膜，形成栅极绝缘膜和栅电极，所述栅极绝缘膜和栅电极层叠在氧化物半导体薄膜的第一区域上 ，并且从所述栅极绝缘膜暴露所述氧化物半导体薄膜的第二区域和第三区域，所述第二区域和所述第三区域位于所述氧化物半导体薄膜的所述第一区域的两侧，形成层间绝缘膜 包括硅的悬挂键，覆盖第二区域的层间绝缘膜和氧化物半导体薄膜的第三区域，栅极绝缘膜和栅电极，以及形成源电极和漏电极。