公开(公告)号：US20230014841A1

公开(公告)日：2023-01-19

申请号：US17949385

申请日：2022-09-21

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Masaharu KOBAYASHI ,  Toshiro HIRAMOTO ,  Jixuan WU

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/786

Abstract: A three-dimensional array device with multiple layers in height direction includes a first two-dimensional array circuit located in a first layer; and a second two-dimensional array circuit located in a second layer adjacent to the first layer and overlapped in a plan view with the first two-dimensional array circuit. Each of the first two-dimensional array circuit and the second two-dimensional array circuit has a first wiring group, an input part that inputs signals to the first wiring group, a second wiring group that intersects the first wiring group and an output part that outputs signals from the second wiring group. The output part in the first two-dimensional array circuit is overlapped in a plan view on the input part in the second two-dimensional array circuit and is connected in a signal transferable manner.

公开(公告)号：US20220157833A1

公开(公告)日：2022-05-19

申请号：US17591102

申请日：2022-02-02

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Masaharu KOBAYASHI ,  Fei MO ,  Toshiro HIRAMOTO

IPC: H01L27/1159 ,  H01L27/11597 ,  G11C11/22

Abstract: A ferroelectric memory device comprising a plurality of ferroelectric memory elements. Each of the plurality of ferroelectric memory elements includes a channel layer containing a metal oxide, a ferroelectric layer in contact with the channel layer in which the ferroelectric layer contains hafnium oxide, a first gate electrode facing the channel layer via the ferroelectric layer, an insulating layer facing the ferroelectric layer via the channel layer; and a second gate electrode facing the channel layer via the insulating layer.