公开(公告)号：US20080082789A1

公开(公告)日：2008-04-03

申请号：US11838075

申请日：2007-08-13

申请人： Jack Kang ,  Hsi-Cheng Chu ,  Yu-Chi Chuang

发明人： Jack Kang ,  Hsi-Cheng Chu ,  Yu-Chi Chuang

IPC分类号： G06F9/312

CPC分类号： G06F9/3851 ,  G06F9/4812

摘要： A system, apparatus and method for interrupt handling on a multi-thread processing device are described herein. Embodiments of the present invention provide a multi-thread processing device for interrupt handling including an interrupt block to provide interrupt signals to a fetch block, including a first interrupt signal line corresponding to a first instruction execution thread and a second interrupt signal line corresponding to a second instruction execution thread. In embodiments, the multi-thread processing device may handle interrupts by providing a shared interrupt service routine for multiple threads or by providing each thread its own unique interrupt service routine.

摘要翻译： 这里描述了一种用于多线程处理设备上的中断处理的系统，装置和方法。 本发明的实施例提供一种用于中断处理的多线程处理装置，包括中断块，以向提取块提供中断信号，包括对应于第一指令执行线程的第一中断信号线和对应于第一指令执行线程的第二中断信号线 第二条指令执行线程。 在实施例中，多线程处理设备可以通过为多个线程提供共享中断服务程序或通过为每个线程提供其自己的唯一中断服务程序来处理中断。

公开(公告)号：US08082427B1

公开(公告)日：2011-12-20

申请号：US12831984

申请日：2010-07-07

申请人： Jack Kang ,  Hsi-Cheng Chu ,  Yu-Chi Chuang

发明人： Jack Kang ,  Hsi-Cheng Chu ,  Yu-Chi Chuang

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/40

CPC分类号： G06F9/3836 ,  G06F9/30101 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/52

摘要： A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.

摘要翻译： 这里描述了一种用于多线程处理设备上的多线程处理的系统，装置和方法。 本发明的实施例提供了一种用于多线程处理的多线程处理设备，包括可操作地耦合到指令分派块的多个寄存器，包括用于选择性地禁用线程的线程控制寄存器。 在各种实施例中，多线程处理设备可以包括线程操作寄存器，用于选择性地向第一线程提供锁定，以防止在第一线程具有锁定时第二线程禁用第一线程。 在另外的实施例中，多线程处理设备可以被配置为原子地禁用和释放由线程保持的锁定。 可以描述和要求保护其他实施例。

公开(公告)号：US08473728B2

公开(公告)日：2013-06-25

申请号：US13479788

申请日：2012-05-24

申请人： Jack Kang ,  Hsi-Cheng Chu ,  Yu-Chi Chuang

发明人： Jack Kang ,  Hsi-Cheng Chu ,  Yu-Chi Chuang

IPC分类号： G06F9/40

CPC分类号： G06F9/3851 ,  G06F9/4812

摘要： Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.

摘要翻译： 用于处理多线程处理环境中多个指令线程的中断的技术。 这些技术包括：交织地取出并发出（i）第一指令执行线程和（ii）第二指令线程的指令，用于由多线程处理环境的执行块执行; 通过所述多线程处理环境内的第一中断信号线提供第一中断信号，以中断所述第一指令执行线程的指令的取出和发出; 以及经由所述多线程处理环境内的第二中断信号线提供第二中断信号，以中断所述第二指令执行线程的指令的取出和发出。 第一个中断信号线和第二个中断信号线是物理上分离的，彼此直接电耦合的不同的信号线。

公开(公告)号：US07757070B1

公开(公告)日：2010-07-13

申请号：US11775444

申请日：2007-07-10

申请人： Jack Kang ,  Hsi-Cheng Chu ,  Yu-Chi Chuang

发明人： Jack Kang ,  Hsi-Cheng Chu ,  Yu-Chi Chuang

IPC分类号： G06F9/00

CPC分类号： G06F9/3836 ,  G06F9/30101 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/52

摘要： A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.

摘要翻译： 这里描述了一种用于多线程处理设备上的多线程处理的系统，装置和方法。 本发明的实施例提供了一种用于多线程处理的多线程处理设备，包括可操作地耦合到指令分派块的多个寄存器，包括用于选择性地禁用线程的线程控制寄存器。 在各种实施例中，多线程处理设备可以包括线程操作寄存器，用于选择性地向第一线程提供锁定，以防止在第一线程具有锁定时第二线程禁用第一线程。 在另外的实施例中，多线程处理设备可以被配置为原子地禁用和释放由线程保持的锁定。 可以描述和要求保护其他实施例。

公开(公告)号：US08478971B1

公开(公告)日：2013-07-02

申请号：US13330305

申请日：2011-12-19

申请人： Jack Kang ,  Yu-Chi Chuang ,  Hsi-Cheng Chu

发明人： Jack Kang ,  Yu-Chi Chuang ,  Hsi-Cheng Chu

IPC分类号： G06F9/00

CPC分类号： G06F9/3836 ,  G06F9/30101 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/52

摘要： A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.

摘要翻译： 这里描述了一种用于多线程处理设备上的多线程处理的系统，装置和方法。 本发明的实施例提供了一种用于多线程处理的多线程处理设备，包括可操作地耦合到指令分派块的多个寄存器，包括用于选择性地禁用线程的线程控制寄存器。 在各种实施例中，多线程处理设备可以包括线程操作寄存器，用于选择性地向第一线程提供锁定，以防止在第一线程具有锁定时第二线程禁用第一线程。 在另外的实施例中，多线程处理设备可以被配置为原子地禁用和释放由线程保持的锁定。 可以描述和要求保护其他实施例。

公开(公告)号：US07870372B2

公开(公告)日：2011-01-11

申请号：US11838075

申请日：2007-08-13

申请人： Jack Kang ,  Hsi-Cheng Chu ,  Yu-Chi Chuang

发明人： Jack Kang ,  Hsi-Cheng Chu ,  Yu-Chi Chuang

IPC分类号： G06F9/00 ,  G06F9/44 ,  G06F15/76

CPC分类号： G06F9/3851 ,  G06F9/4812

摘要： A system, apparatus and method for interrupt handling on a multi-thread processing device are described herein. Embodiments of the present invention provide a multi-thread processing device for interrupt handling including an interrupt block to provide interrupt signals to a fetch block, including a first interrupt signal line corresponding to a first instruction execution thread and a second interrupt signal line corresponding to a second instruction execution thread. In embodiments, the multi-thread processing device may handle interrupts by providing a shared interrupt service routine for multiple threads or by providing each thread its own unique interrupt service routine.

摘要翻译： 这里描述了一种用于多线程处理设备上的中断处理的系统，装置和方法。 本发明的实施例提供一种用于中断处理的多线程处理装置，包括中断块，以向提取块提供中断信号，包括对应于第一指令执行线程的第一中断信号线和对应于第一指令执行线程的第二中断信号线 第二条指令执行线程。 在实施例中，多线程处理设备可以通过为多个线程提供共享中断服务程序或通过为每个线程提供其自己的唯一中断服务程序来处理中断。

公开(公告)号：US08190866B2

公开(公告)日：2012-05-29

申请号：US12987716

申请日：2011-01-10

申请人： Jack Kang ,  Hsi-Cheng Chu ,  Yu-Chi Chuang

发明人： Jack Kang ,  Hsi-Cheng Chu ,  Yu-Chi Chuang

IPC分类号： G06F9/00 ,  G06F9/44 ,  G06F15/76

CPC分类号： G06F9/3851 ,  G06F9/4812

摘要： Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.

摘要翻译： 用于处理多线程处理环境中多个指令线程的中断的技术。 这些技术包括：交织地取出并发出（i）第一指令执行线程和（ii）第二指令线程的指令，用于由多线程处理环境的执行块执行; 通过所述多线程处理环境内的第一中断信号线提供第一中断信号，以中断所述第一指令执行线程的指令的取出和发出; 以及经由所述多线程处理环境内的第二中断信号线提供第二中断信号，以中断所述第二指令执行线程的指令的取出和发出。 第一个中断信号线和第二个中断信号线是物理上分离的，彼此直接电耦合的不同的信号线。

公开(公告)号：US08478972B2

公开(公告)日：2013-07-02

申请号：US13247030

申请日：2011-09-28

申请人： Jack Kang ,  Hsi-Cheng Chu

发明人： Jack Kang ,  Hsi-Cheng Chu

IPC分类号： G06F9/40

CPC分类号： G06F9/3851 ,  G06F9/463 ,  G06F9/485

摘要： A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution during a cycle count associated with the first instruction execution thread and when the instruction execution thread is in an active mode. The method further includes switching a second instruction execution thread to the active mode when the cycle count corresponding to the first instruction execution thread is complete, and fetching and issuing one or more instructions, corresponding to the second instruction execution thread, to the execution block for execution during a cycle count associated with the second instruction execution thread. The method additionally includes resetting the cycle counts when a master instruction execution thread is in the active mode.

摘要翻译： 本文描述了一种用于处理多线程处理器内的线程之间的切换的系统，装置和方法。 本发明的实施例提供了一种用于多线程处理的方法，包括将与第一指令执行线程相对应的一个或多个指令发送到执行块，以在与第一指令执行线程相关联的周期计数期间执行，并且当指令 执行线程处于活动模式。 该方法还包括当与第一指令执行线程相对应的周期计数完成时将第二指令执行线程切换到活动模式，并且将对应于第二指令执行线程的一个或多个指令取出并发出到执行块 在与第二指令执行线程相关联的周期计数期间执行。 该方法还包括当主指令执行线程处于活动模式时重置周期计数。

公开(公告)号：US08032737B2

公开(公告)日：2011-10-04

申请号：US11836044

申请日：2007-08-08

申请人： Jack Kang ,  Hsi-Cheng Chu

发明人： Jack Kang ,  Hsi-Cheng Chu

IPC分类号： G06F9/00

CPC分类号： G06F9/3851 ,  G06F9/463 ,  G06F9/485

摘要： A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution during a cycle count associated with the first instruction execution thread and when the instruction execution thread is in an active mode. The method further includes switching a second instruction execution thread to the active mode when the cycle count corresponding to the first instruction execution thread is complete, and fetching and issuing one or more instructions, corresponding to the second instruction execution thread, to the execution block for execution during a cycle count associated with the second instruction execution thread. The method additionally includes resetting the cycle counts when a master instruction execution thread is in the active mode. Other embodiments may be described and claimed.

摘要翻译： 本文描述了一种用于处理多线程处理器内的线程之间的切换的系统，装置和方法。 本发明的实施例提供了一种用于多线程处理的方法，包括将与第一指令执行线程相对应的一个或多个指令发送到执行块，以在与第一指令执行线程相关联的周期计数期间执行，并且当指令 执行线程处于活动模式。 该方法还包括当与第一指令执行线程相对应的周期计数完成时将第二指令执行线程切换到活动模式，并且将对应于第二指令执行线程的一个或多个指令取出并发出到执行块 在与第二指令执行线程相关联的周期计数期间执行。 该方法还包括当主指令执行线程处于活动模式时重置周期计数。 可以描述和要求保护其他实施例。

公开(公告)号：US20080040579A1

公开(公告)日：2008-02-14

申请号：US11836044

申请日：2007-08-08

申请人： Jack Kang ,  Hsi-Cheng Chu

发明人： Jack Kang ,  Hsi-Cheng Chu

IPC分类号： G06F9/312

CPC分类号： G06F9/3851 ,  G06F9/463 ,  G06F9/485

摘要： A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution during a cycle count associated with the first instruction execution thread and when the instruction execution thread is in an active mode. The method further includes switching a second instruction execution thread to the active mode when the cycle count corresponding to the first instruction execution thread is complete, and fetching and issuing one or more instructions, corresponding to the second instruction execution thread, to the execution block for execution during a cycle count associated with the second instruction execution thread. The method additionally includes resetting the cycle counts when a master instruction execution thread is in the active mode. Other embodiments may be described and claimed.

摘要翻译： 本文描述了一种用于处理多线程处理器内的线程之间的切换的系统，装置和方法。 本发明的实施例提供了一种用于多线程处理的方法，包括将与第一指令执行线程相对应的一个或多个指令发送到执行块，以在与第一指令执行线程相关联的周期计数期间执行，并且当指令 执行线程处于活动模式。 该方法还包括当与第一指令执行线程相对应的周期计数完成时，将第二指令执行线程切换到激活模式，并且将对应于第二指令执行线程的一个或多个指令取出并发出到执行块 在与第二指令执行线程相关联的周期计数期间执行。 该方法还包括当主指令执行线程处于活动模式时重置周期计数。 可以描述和要求保护其他实施例。