摘要:
Data locality optimization through object relocation may be implemented in a virtual machine including a just-in-time compiler. The just-in-time compiler generates load instruction maps for each compiled method. A profile collector is coupled to the just-in-time compiler to receive hardware profiling support. The profile collector takes samples of data cache misses. A garbage collector is coupled to the profile collector. The garbage collector deduces types of objects from the cache miss samples and adjusts garbage collection object copying heuristics to relocate objects for better cache locality based on those types.
摘要:
Data locality optimization through object relocation may be implemented in a virtual machine including a just-in-time compiler. The just-in-time compiler generates load instruction maps for each compiled method. A profile collector is coupled to the just-in-time compiler to receive hardware profiling support. The profile collector takes samples of data cache misses. A garbage collector is coupled to the profile collector. The garbage collector deduces types of objects from the cache miss samples and adjusts garbage collection object copying heuristics to relocate objects for better cache locality based on those types.
摘要:
A method and apparatus that provides instruction re-alignment using a branch on a falsehood of a qualifying predicate. A complementary predicate related to a qualifying predicate is determined to be available. Instructions are re-aligned using a branch on a falsehood of the qualifying predicate if the complementary predicate is not available. Thus, a complementary predicate does not have to be generated to re-align instructions if no complementary predicate is available for the qualifying predicate.
摘要:
A compiler or runt-time system may determine a prefetch point to insert an instruction in order to prefetch a memory location and thereby reduce latency in accessing information from a cache. A prefetch predictor generator may decide where and whether to insert the appropriate instructions by looking at information from a hardware monitor. For example, information about cache misses may be analyzed. The differences between target addresses of those cache misses for different instructions may be determined. This information may also be used to determine the locations in the program where the prefetch instructions should be placed, as well as to calculate the address of the memory location being prefetched.
摘要:
A compiler comprising an integrated instruction scheduler and resource management system is provided. According to an aspect of an embodiment, the resource management system includes a function unit based finite state automata system. Instructions to be compiled are modeled through the function unit based finite state automata system based on their function unit usage, before they are emitted as compiled computer code. We also disclose a function unit based finite state automata data structure and computer implemented methods for making the same.
摘要:
In one embodiment, a method is provided. The method of this embodiment provides reading one or more records event data, the one or more event data corresponding to an event monitored from a system; for each event datum, compressing the event datum if the event datum is determined to be compressible; creating a processed event record, the processed event record conforming to a record format; and storing the one or more event data in the processed event record in accordance with the record format.
摘要:
We disclose a function unit based finite state automata data structure for use in computer program compilers. According to an aspect of an embodiment, the data structure comprises a function unit vector, having no more used bits than there are issue ports for any particular microprocessor, and a plurality of valid template assignments for each function unit vector. In a preferred embodiment, the template assignments are constructed so as to account for dispersal rules associated with the particular microprocessor. Further, the template assignments can be sorted according to priority data.
摘要:
The invention is directed to the transformation of software loops having early exit conditions, thereby allowing the loops to be more effectively converted to a single basic block for software pipelining. The invention assigns a predicate register for each early exit condition of the software loop. The predicate registers are set when the corresponding early exit condition is satisfied. In this manner, when the loop terminates the predicate registers can be examined to indicate which early exit conditions were satisfied. The invention produces loops having a lower recurrence II and resource II than conventional techniques.
摘要:
Disclosed are a method, apparatus and system for dynamically managing layout of compiled code in a managed runtime environment. Profile feedback is generated during runtime, based on hardware event data that is gathered during runtime. A code manager dynamically relocates compiled code to reduce miss events based on the profile feedback. The code manager may also relocate virtual method tables in a virtual table region in order to reduce data miss events. The method does not require a prior run of an application program because profile feedback is based on event data that is tracked by hardware during execution of the software application and is not based on instrumented code.
摘要:
Disclosed are a method, apparatus and system for dynamically managing layout of compiled code in a managed runtime environment. Profile feedback is generated during runtime, based on hardware event data that is gathered during runtime. A code manager dynamically relocates compiled code to reduce miss events based on the profile feedback. The code manager may also relocate virtual method tables in a virtual table region in order to reduce data miss events. The method does not require a prior run of an application program because profile feedback is based on event data that is tracked by hardware during execution of the software application and is not based on instrumented code.