公开(公告)号：US5479420A

公开(公告)日：1995-12-26

申请号：US173177

申请日：1993-12-28

申请人： Jae H. Hong ,  Dong J. Shin ,  Youn K. Jeong ,  Hyeong J. Park

发明人： Jae H. Hong ,  Dong J. Shin ,  Youn K. Jeong ,  Hyeong J. Park

IPC分类号： G06F1/04 ,  G06F11/00 ,  H04L7/00 ,  G11B27/00

CPC分类号： G06F11/0757 ,  G06F1/04 ,  H04L7/0083

摘要： A circuit for determining whether a digital circuit clock is operating normally. It includes a monitoring clock receiver for receiving a monitoring clock signal, a counter reset generator which generates a first reset signal in response to the monitoring clock signal, and a reset signal receiver for receiving a second reset signal and synchronizing the second reset signal with the monitoring clock signal. The second reset signal is also used to initialize a digital circuit pack upon power-on. The circuit further includes a monitoring counter circuit for sampling and counting a reference clock signal in response to the first and second reset signals to monitor the monitoring clock signal. The reference clock signal has a frequency twice that of the monitoring clock signal. A NAND logic unit is provided for outputting the monitored result in response to an output signal from the monitoring counter circuit so that the user can determine a clock error according to the monitored result. An output hold circuit is further provided for holding the monitored result from the NAND logic unit when the monitoring clock signal is abnormal.

摘要翻译： 用于确定数字电路时钟是否正常工作的电路。 它包括用于接收监控时钟信号的监视时钟接收器，响应监视时钟信号产生第一复位信号的计数器复位发生器，以及用于接收第二复位信号并使第二复位信号与第二复位信号同步的复位信号接收器 监控时钟信号。 第二复位信号也用于在通电时初始化数字电路板。 该电路还包括监视计数器电路，用于响应于第一和第二复位信号对参考时钟信号进行采样和计数，以监视监控时钟信号。 参考时钟信号的频率是监视时钟信号的两倍。 提供NAND逻辑单元，用于响应于来自监视计数器电路的输出信号输出监视结果，使得用户可以根据监视结果确定时钟误差。 另外还提​​供一个输出保持电路，用于当监视时钟信号异常时保持来自NAND逻辑单元的监视结果。