公开(公告)号：US07297584B2

公开(公告)日：2007-11-20

申请号：US11246471

申请日：2005-10-07

申请人： Jae-Eon Park ,  Ja-Hum Ku ,  Jun-Jung Kim ,  Dae-Kwon Kang ,  Young Way Teh

发明人： Jae-Eon Park ,  Ja-Hum Ku ,  Jun-Jung Kim ,  Dae-Kwon Kang ,  Young Way Teh

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/268 ,  H01L21/3185 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/7843

摘要： In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.

摘要翻译： 在具有用于改善电子迁移率的双应力衬垫的半导体器件中，双应力衬垫包括形成在PMOSFET上的第一衬垫部分和形成在NMOSFET上的第二衬垫部分。 第一衬里部分具有第一压缩应力，并且第二衬套部分具有小于第一压缩应力的第二压缩应力。 双应力衬垫可以通过在其上形成PMOSFET和NMOSFET的半导体衬底上形成应力衬垫而形成，并且选择性地暴露在NMOSFET上的应力衬垫的一部分。

公开(公告)号：US20080029823A1

公开(公告)日：2008-02-07

申请号：US11870573

申请日：2007-10-11

申请人： Jae-Eon Park ,  Ja-Hum Ku ,  Jun-Jung Kim ,  Dae-Kwon Kang ,  Young Teh

发明人： Jae-Eon Park ,  Ja-Hum Ku ,  Jun-Jung Kim ,  Dae-Kwon Kang ,  Young Teh

IPC分类号： H01L29/94 ,  G21G5/00

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/268 ,  H01L21/3185 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/7843

摘要： In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.

摘要翻译： 在具有用于改善电子迁移率的双应力衬垫的半导体器件中，双应力衬垫包括形成在PMOSFET上的第一衬垫部分和形成在NMOSFET上的第二衬垫部分。 第一衬里部分具有第一压缩应力，并且第二衬套部分具有小于第一压缩应力的第二压缩应力。 双应力衬垫可以通过在其上形成PMOSFET和NMOSFET的半导体衬底上形成应力衬垫而形成，并且选择性地暴露在NMOSFET上的应力衬垫的一部分。

公开(公告)号：US20070082439A1

公开(公告)日：2007-04-12

申请号：US11246471

申请日：2005-10-07

申请人： Jae-Eon Park ,  Ja-Hum Ku ,  Jun-Jung Kim ,  Dae-Kwon Kang ,  Young Teh

发明人： Jae-Eon Park ,  Ja-Hum Ku ,  Jun-Jung Kim ,  Dae-Kwon Kang ,  Young Teh

IPC分类号： H01L21/8238 ,  H01L29/788

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/268 ,  H01L21/3185 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/7843

摘要： In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.

摘要翻译： 在具有用于改善电子迁移率的双应力衬垫的半导体器件中，双应力衬垫包括形成在PMOSFET上的第一衬垫部分和形成在NMOSFET上的第二衬垫部分。 第一衬里部分具有第一压缩应力，并且第二衬套部分具有小于第一压缩应力的第二压缩应力。 双应力衬垫可以通过在其上形成PMOSFET和NMOSFET的半导体衬底上形成应力衬垫而形成，并且选择性地暴露在NMOSFET上的应力衬垫的一部分。

公开(公告)号：US20100167533A1

公开(公告)日：2010-07-01

申请号：US12647806

申请日：2009-12-28

申请人： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

发明人： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7843

摘要： A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer.

摘要翻译： 制造半导体集成电路（IC）器件的方法可以包括在衬底上的晶体管的至少一部分上形成第一硅化物层，在第一硅化物层中形成氮以形成第二硅化物层，形成第一应力层 在其上形成有晶体管的衬底上具有拉伸应力，并且用紫外线（UV）光照射第一应力层以形成具有比第一应力层更大的拉伸应力的第二应力层。

公开(公告)号：US10229876B2

公开(公告)日：2019-03-12

申请号：US15073640

申请日：2016-03-17

申请人： Jun-Jung Kim ,  Young-Bae Kim ,  Jong-Sam Kim ,  Jin-Hyeung Park ,  Jeong-Hoon Ahn ,  Hyeok-Sang Oh ,  Kyoung-Woo Lee ,  Hyo-Seon Lee ,  Suk-Hee Jang

发明人： Jun-Jung Kim ,  Young-Bae Kim ,  Jong-Sam Kim ,  Jin-Hyeung Park ,  Jeong-Hoon Ahn ,  Hyeok-Sang Oh ,  Kyoung-Woo Lee ,  Hyo-Seon Lee ,  Suk-Hee Jang

IPC分类号： H01L23/535 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485

摘要： A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.

公开(公告)号：US08227308B2

公开(公告)日：2012-07-24

申请号：US12647806

申请日：2009-12-28

申请人： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

发明人： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

IPC分类号： H01L21/8238

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7843

摘要： A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer.

摘要翻译： 制造半导体集成电路（IC）器件的方法可以包括在衬底上的晶体管的至少一部分上形成第一硅化物层，在第一硅化物层中形成氮以形成第二硅化物层，形成第一应力层 在其上形成有晶体管的衬底上具有拉伸应力，并且用紫外线（UV）光照射第一应力层以形成具有比第一应力层更大的拉伸应力的第二应力层。