公开(公告)号：US20160148930A1

公开(公告)日：2016-05-26

申请号：US15009276

申请日：2016-01-28

申请人： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

发明人： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC分类号： H01L27/088 ,  H01L29/10 ,  H01L27/02 ,  H01L29/165 ,  H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

公开(公告)号：US20150214329A1

公开(公告)日：2015-07-30

申请号：US14680349

申请日：2015-04-07

申请人： Dong-Suk SHIN ,  Hyun-Chul KANG ,  Dong-Hyun ROH ,  Pan-Kwi PARK ,  Geo-Myung SHIN ,  Nae-In LEE ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM

发明人： Dong-Suk SHIN ,  Hyun-Chul KANG ,  Dong-Hyun ROH ,  Pan-Kwi PARK ,  Geo-Myung SHIN ,  Nae-In LEE ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM

IPC分类号： H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

摘要翻译： 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成沟槽，并且沟槽可以包括有源区的切口部分。 所述方法还可以包括在沟槽中形成嵌入的应力源。 嵌入式应力器可以包括下半导体层和上半导体层，其宽度比下半导体层的宽度窄。 上半导体层的一侧可以不与下半导体层的一侧对准，并且上半导体层的最上表面可以高于有源区的最上表面。

公开(公告)号：US08772173B2

公开(公告)日：2014-07-08

申请号：US13461088

申请日：2012-05-01

申请人： Hyun-kwan Yu ,  Dong-suk Shin ,  Pan-kwi Park ,  Ki-eun Kim

发明人： Hyun-kwan Yu ,  Dong-suk Shin ,  Pan-kwi Park ,  Ki-eun Kim

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/823807 ,  H01L21/28518 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/665 ,  H01L29/7843

摘要： A method of manufacturing a semiconductor device includes providing a substrate having a gate structure, a source region, and a drain region formed thereon, and the gate structure includes a gate insulating layer and a gate electrode. The method also includes forming a first stress layer on the substrate, removing the first stress layer, and forming a second stress layer on the substrate.

摘要翻译： 制造半导体器件的方法包括提供具有形成在其上的栅极结构，源极区和漏极区的衬底，并且栅极结构包括栅极绝缘层和栅电极。 该方法还包括在衬底上形成第一应力层，去除第一应力层，以及在衬底上形成第二应力层。

公开(公告)号：US08227308B2

公开(公告)日：2012-07-24

申请号：US12647806

申请日：2009-12-28

申请人： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

发明人： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

IPC分类号： H01L21/8238

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7843

摘要： A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer.

摘要翻译： 制造半导体集成电路（IC）器件的方法可以包括在衬底上的晶体管的至少一部分上形成第一硅化物层，在第一硅化物层中形成氮以形成第二硅化物层，形成第一应力层 在其上形成有晶体管的衬底上具有拉伸应力，并且用紫外线（UV）光照射第一应力层以形成具有比第一应力层更大的拉伸应力的第二应力层。

公开(公告)号：US20110018044A1

公开(公告)日：2011-01-27

申请号：US12841245

申请日：2010-07-22

申请人： HA-JIN LIM ,  Pan-Kwi Park ,  Dong-Suk Shin

发明人： HA-JIN LIM ,  Pan-Kwi Park ,  Dong-Suk Shin

IPC分类号： H01L29/78 ,  H01L29/94 ,  H01L27/092 ,  H01L21/31

CPC分类号： H01L29/76 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/7843

摘要： A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress.

摘要翻译： 半导体器件包括MOSFET和设置在MOSFET上的多个应力层，其中应力层包括设置在MOSFET上的第一应力层和设置在第一应力层上的第二应力层，第一应力层具有第一应力层 应力和第二应力层具有第二应力，并且第一应力不同于第二应力。

公开(公告)号：US20090233434A1

公开(公告)日：2009-09-17

申请号：US12401305

申请日：2009-03-10

申请人： Weon-Hong KIM ,  Min-woo Song ,  Pan-Kwi Park ,  Jung-Min Park

发明人： Weon-Hong KIM ,  Min-woo Song ,  Pan-Kwi Park ,  Jung-Min Park

IPC分类号： H01L21/4763 ,  H01L21/469

CPC分类号： C23C16/308 ,  C23C16/30 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45542 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31641 ,  H01L28/55

摘要： In semiconductor devices and methods of manufacturing semiconductor devices, a zirconium source having zirconium, carbon and nitrogen is provided onto a substrate to form an adsorption layer of the zirconium source on the substrate. A first purging process is performed to remove a non-adsorbed portion of the zirconium source. An oxidizing gas is provided onto the adsorption layer to form an oxidized adsorption layer of the zirconium source on the substrate. A second purging process is performed to remove a non-reacted portion of the oxidizing gas. A nitriding gas is provided on the oxidized adsorption layer to form a zirconium carbo-oxynitride layer on the substrate, and a third purging process is provided to remove a non-reacted portion of the nitriding gas.

摘要翻译： 在制造半导体器件的半导体器件和方法中，将具有锆，碳和氮的锆源提供到衬底上以在衬底上形成锆源的吸附层。 进行第一吹扫处理以除去锆源的未吸附部分。 在吸附层上提供氧化气体，以在衬底上形成锆源的氧化吸附层。 执行第二吹扫处理以除去氧化气体的未反应部分。 在氧化吸附层上设置氮化气体，在基板上形成锆碳氮化锆层，并且提供第三吹扫工艺以去除氮化气体的未反应部分。

公开(公告)号：US09583592B2

公开(公告)日：2017-02-28

申请号：US14697266

申请日：2015-04-27

申请人： Pan-Kwi Park ,  Dong-Suk Shin ,  Seok-Jun Won ,  Weon-Hong Kim ,  Jae-Gon Lee

发明人： Pan-Kwi Park ,  Dong-Suk Shin ,  Seok-Jun Won ,  Weon-Hong Kim ,  Jae-Gon Lee

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/8234

CPC分类号： H01L29/66545 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02332 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

摘要： In a method of manufacturing a semiconductor device, a dummy gate structure is formed on a substrate. A first spacer layer is formed on the substrate to cover the dummy gate structure. A nitridation process is performed on the first spacer layer. An upper portion of the substrate adjacent to the dummy gate structure is removed to form a trench. An inner wall of the trench is cleaned. An epitaxial layer is formed to fill the trench. The dummy gate structure is replaced with a gate structure.

摘要翻译： 在制造半导体器件的方法中，在基板上形成虚拟栅极结构。 在衬底上形成第一间隔层以覆盖虚拟栅极结构。 在第一间隔层上进行氮化处理。 去除与伪栅极结构相邻的衬底的上部以形成沟槽。 清洁沟槽的内壁。 形成外延层以填充沟槽。 虚拟栅极结构被栅极结构代替。

公开(公告)号：US20130320434A1

公开(公告)日：2013-12-05

申请号：US13908440

申请日：2013-06-03

申请人： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

发明人： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

IPC分类号： H01L29/78

CPC分类号： H01L27/1104 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28247 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7827 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

摘要： In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

摘要翻译： 在半导体器件中，第一有源区具有第一西格玛形状，第二有源区具有第二西格玛形状。 当垂直于衬底并将第一栅电极的侧表面通过第一区域的线被定义为第一垂直线时，当垂直于衬底并通过第二栅电极的侧表面的线 在第二区域被定义为第二垂直线时，当第一垂直线和第一沟槽之间的最短距离被定义为第一水平距离时，并且当第二垂直线和第二沟槽之间的最短距离被定义为 第二水平距离，第一水平距离和第二水平距离之间的差等于或小于1nm。

公开(公告)号：US20160197188A1

公开(公告)日：2016-07-07

申请号：US15071502

申请日：2016-03-16

申请人： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

发明人： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

IPC分类号： H01L29/78 ,  H01L29/51 ,  H01L27/11 ,  H01L29/45 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165

CPC分类号： H01L27/1104 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28247 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7827 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

摘要： In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

公开(公告)号：US20100167533A1

公开(公告)日：2010-07-01

申请号：US12647806

申请日：2009-12-28

申请人： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

发明人： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7843

摘要： A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer.

摘要翻译： 制造半导体集成电路（IC）器件的方法可以包括在衬底上的晶体管的至少一部分上形成第一硅化物层，在第一硅化物层中形成氮以形成第二硅化物层，形成第一应力层 在其上形成有晶体管的衬底上具有拉伸应力，并且用紫外线（UV）光照射第一应力层以形成具有比第一应力层更大的拉伸应力的第二应力层。