公开(公告)号：US20090239369A1

公开(公告)日：2009-09-24

申请号：US12051223

申请日：2008-03-19

申请人： Jae-hak Kim ,  Jing Hui Li ,  Wu Ping Liu ,  Johnny Widodo

发明人： Jae-hak Kim ,  Jing Hui Li ,  Wu Ping Liu ,  Johnny Widodo

IPC分类号： H01L21/31 ,  H01L21/44

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76814 ,  H01L2221/1063

摘要： Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.

摘要翻译： 形成具有电互连的集成电路器件的方法包括在衬底上形成电绝缘层并在电绝缘层上形成硬掩模。 使用掩模依次选择性地蚀刻硬掩模和电绝缘层，以在其中限定开口。 该开口（其可以是通孔）暴露硬掩模和电绝缘层的内侧壁。 然后硬掩模的内侧壁相对于电绝缘层的内侧壁凹陷，并且牺牲反应层形成在电绝缘层的内侧壁上。 该反应层操作以使电绝缘层的内侧壁凹陷。 然后去除反应层以限定具有相对均匀侧壁的较宽开口。 然后用更宽的开口填充电互连。

公开(公告)号：US07687381B2

公开(公告)日：2010-03-30

申请号：US12051223

申请日：2008-03-19

申请人： Jae-hak Kim ,  Jing Hui Li ,  Wu Ping Liu ,  Johnny Widodo

发明人： Jae-hak Kim ,  Jing Hui Li ,  Wu Ping Liu ,  Johnny Widodo

IPC分类号： H01L21/46 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76814 ,  H01L2221/1063

摘要： Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.

摘要翻译： 形成具有电互连的集成电路器件的方法包括在衬底上形成电绝缘层并在电绝缘层上形成硬掩模。 使用掩模依次选择性地蚀刻硬掩模和电绝缘层，以在其中限定开口。 该开口（其可以是通孔）暴露硬掩模和电绝缘层的内侧壁。 然后硬掩模的内侧壁相对于电绝缘层的内侧壁凹陷，并且牺牲反应层形成在电绝缘层的内侧壁上。 该反应层操作以使电绝缘层的内侧壁凹陷。 然后去除反应层以限定具有相对均匀侧壁的较宽开口。 然后用更宽的开口填充电互连。

公开(公告)号：US09281278B2

公开(公告)日：2016-03-08

申请号：US13286224

申请日：2011-11-01

申请人： Jing Hui Li ,  Wu Ping Liu ,  Lawrence A. Clevenger

发明人： Jing Hui Li ,  Wu Ping Liu ,  Lawrence A. Clevenger

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

摘要翻译： 提出了一种形成半导体器件的方法。 提供了在其上形成有介电层的基板。 在介电层上形成第一上蚀刻停止层。 第一上蚀刻停止层包括第一电介质材料。 将电介质层和第一上蚀刻停止层图案化以形成互连开口。 互连开口填充有导电材料以形成互连。 互连和第一上蚀刻停止层具有共面的顶表面。 第二上蚀刻停止层形成在共面顶表面上。 第二上蚀刻停止层包括与第一材料具有足够粘合力以减少导电材料扩散的第二材料。

公开(公告)号：US08053361B2

公开(公告)日：2011-11-08

申请号：US12203924

申请日：2008-09-04

申请人： Jing Hui Li ,  Wu Ping Liu ,  Lawrence A. Clevenger

发明人： Jing Hui Li ,  Wu Ping Liu ,  Lawrence A. Clevenger

IPC分类号： H01L23/52

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

摘要翻译： 提出了一种形成半导体器件的方法。 提供了在其上形成有介电层的基板。 在介电层上形成第一上蚀刻停止层。 第一上蚀刻停止层包括第一电介质材料。 将电介质层和第一上蚀刻停止层图案化以形成互连开口。 互连开口填充有导电材料以形成互连。 互连和第一上蚀刻停止层具有共面的顶表面。 第二上蚀刻停止层形成在共面顶表面上。 第二上蚀刻停止层包括与第一材料具有足够粘合力以减少导电材料扩散的第二材料。

公开(公告)号：US08143166B2

公开(公告)日：2012-03-27

申请号：US12046151

申请日：2008-03-11

申请人： Feng Zhao ,  Wu Ping Liu ,  John Sudijono ,  Laertis Economikos ,  Lawrence A. Clevenger

发明人： Feng Zhao ,  Wu Ping Liu ,  John Sudijono ,  Laertis Economikos ,  Lawrence A. Clevenger

IPC分类号： H01L21/461

CPC分类号： H01L21/31053 ,  H01L21/3212

摘要： A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.

摘要翻译： 在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。 在抛光过程中，气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。 惰性气泡密度在被抛光的基底的表面区域附近动态增加，这些表面区域易于发生凹陷和侵蚀。 增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。 抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率，使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。

公开(公告)号：US20090233444A1

公开(公告)日：2009-09-17

申请号：US12046151

申请日：2008-03-11

申请人： Feng Zhao ,  Wu Ping Liu ,  John Sudijono ,  Laertis Economikos ,  Lawrence A. Clevenger

发明人： Feng Zhao ,  Wu Ping Liu ,  John Sudijono ,  Laertis Economikos ,  Lawrence A. Clevenger

IPC分类号： H01L21/306 ,  C09K13/00

CPC分类号： H01L21/31053 ,  H01L21/3212

摘要： A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.

摘要翻译： 在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。 在抛光过程中，气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。 惰性气泡密度在被抛光的基底的表面区域附近动态增加，这些表面区域易于发生凹陷和侵蚀。 增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。 抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率，使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。