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1.发明申请Semiconductor memory device including post package repair control circuit and post package repair method 失效半导体存储器件包括后封装修复控制电路和后封装修复方法公开(公告)号：US20080247243A1
公开(公告)日：2008-10-09
申请号：US12080728
申请日：2008-04-04
申请人： Jae-sung Kang , Byung-heon Kwak , Hyun-soon Jang , Seung-whan Seo , Sang-joon Ryu , Hyun-tae Lim
发明人： Jae-sung Kang , Byung-heon Kwak , Hyun-soon Jang , Seung-whan Seo , Sang-joon Ryu , Hyun-tae Lim
CPC分类号： G11C29/70
摘要： Provided are a semiconductor memory device having a post package repair control circuit and a post package repair method. In the semiconductor memory device and the post package repair method, in a post package repair mode, a second memory bank is used as a fail bit map memory for storing failed bit information regarding a first memory bank, and the first memory bank is used as a fail bit map memory for storing failed bit information regarding the second memory bank.
摘要翻译： 提供了一种具有后封装修复控制电路和后封装修复方法的半导体存储器件。 在半导体存储器件和后封装修复方法中，在后封装修复模式中，第二存储体被用作用于存储关于第一存储体的故障位信息的故障位图存储器，并且第一存储体被用作 用于存储关于第二存储体的失败位信息的故障位图存储器。
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2.发明授权Semiconductor memory device including post package repair control circuit and post package repair method 失效半导体存储器件包括后封装修复控制电路和后封装修复方法公开(公告)号：US07746712B2
公开(公告)日：2010-06-29
申请号：US12080728
申请日：2008-04-04
申请人： Jae-sung Kang , Byung-heon Kwak , Hyun-soon Jang , Seung-whan Seo , Sang-joon Ryu , Hyun-tae Lim
发明人： Jae-sung Kang , Byung-heon Kwak , Hyun-soon Jang , Seung-whan Seo , Sang-joon Ryu , Hyun-tae Lim
CPC分类号： G11C29/70
摘要： Provided are a semiconductor memory device having a post package repair control circuit and a post package repair method. In the semiconductor memory device and the post package repair method, in a post package repair mode, a second memory bank is used as a fail bit map memory for storing failed bit information regarding a first memory bank, and the first memory bank is used as a fail bit map memory for storing failed bit information regarding the second memory bank.
摘要翻译： 提供了一种具有后封装修复控制电路和后封装修复方法的半导体存储器件。 在半导体存储器件和后封装修复方法中，在后封装修复模式中，第二存储体被用作用于存储关于第一存储体的故障位信息的故障位图存储器，并且第一存储体被用作 用于存储关于第二存储体的失败位信息的故障位图存储器。
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3.发明授权Parallel bit test apparatus and parallel bit test method capable of reducing test time 失效并行位测试装置和并行位测试方法，能够减少测试时间公开(公告)号：US07941714B2
公开(公告)日：2011-05-10
申请号：US12003900
申请日：2008-01-03
申请人： Yong-hwan Cho , Kwun-soo Cheon , Hyun-soon Jang , Seung-whan Seo
发明人： Yong-hwan Cho , Kwun-soo Cheon , Hyun-soon Jang , Seung-whan Seo
CPC分类号： G11C29/40 , G11C5/04 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/2602
摘要： A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.
摘要翻译： 包含在堆叠在多芯片封装（MCP）中并且共享一组数据信号线的存储器芯片中的并行位测试（PBT）装置可以包括：比较单元，用于输出表示比较的数据信号 分别提供给给定的一个存储器芯片的测试数据信号和从其输出的相应的数据信号之间; 以及编码单元，用于使用所述共享数据信号线组的第一子集输出所述代表数据信号，所述第一子集分别不与由所述存储器芯片中的其他存储器芯片对应的编码单元使用的其他子集重叠，所述编码单元选择 根据第一测试模式寄存器组（MRS）信号将数据信号线的共享数据集中的一个或多个数据信号线包括在第一子集中。
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4.发明申请Parallel bit test apparatus and parallel bit test method capable of reducing test time 失效并行位测试装置和并行位测试方法，能够减少测试时间公开(公告)号：US20080168316A1
公开(公告)日：2008-07-10
申请号：US12003900
申请日：2008-01-03
申请人： Yong-hwan Cho , Kwun-soo Cheon , Hyun-soon Jang , Seung-whan Seo
发明人： Yong-hwan Cho , Kwun-soo Cheon , Hyun-soon Jang , Seung-whan Seo
CPC分类号： G11C29/40 , G11C5/04 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/2602
摘要： A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.
摘要翻译： 包含在堆叠在多芯片封装（MCP）中并且共享一组数据信号线的存储器芯片中的并行位测试（PBT）装置可以包括：比较单元，用于输出表示比较的数据信号 分别提供给给定的一个存储器芯片的测试数据信号和从其输出的相应的数据信号之间; 以及编码单元，用于使用所述共享数据信号线组的第一子集输出所述代表数据信号，所述第一子集分别不与由所述存储器芯片中的其他存储器芯片对应的编码单元使用的其他子集重叠，所述编码单元选择 根据第一测试模式寄存器组（MRS）信号将数据信号线的共享数据集中的一个或多个数据信号线包括在第一子集中。
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