公开(公告)号：US20080307374A1

公开(公告)日：2008-12-11

申请号：US11758277

申请日：2007-06-05

申请人： James C. Gregerson ,  Leonard M. Greenberg ,  Steven J. Hnatko ,  Kirk D. Lamb ,  James H. McCullen

发明人： James C. Gregerson ,  Leonard M. Greenberg ,  Steven J. Hnatko ,  Kirk D. Lamb ,  James H. McCullen

IPC分类号： G06F9/45

CPC分类号： G06F17/5077 ,  G06F17/5031

摘要： A logical design including multiple logical blocks is mapped onto an integrated circuit chip. A chip level floor plan is created on the chip, including temporary areas on the chip set aside for accommodating logical blocks having logical content including timing requirements based on the logical design. The temporary areas are translated into physical cells on the chip with pins assigned for inputs and outputs for the logical blocks. The logical blocks are mapped to the physical cells on the chip in a time sensitive manner using timing assertions to form temporary logical partitions. Blocks on the chip, including the temporary logical partitions, are connected based on the timing assertions. A timing analysis is performed on the chip to determine timing slack associated with each temporary logical partition. A determination is made whether the timing slack is acceptable. If the timing slack is not acceptable, the slack is apportioned for, and apportioned slack information is fed back in the form of timing assertions. Mapping, connecting, performing a timing analysis, and apportioning for slack are repeated until the timing slack associated with each temporary logical partition is determined to be acceptable.

摘要翻译： 包括多个逻辑块的逻辑设计被映射到集成电路芯片上。 在芯片上创建芯片级平面图，包括芯片上的临时区域，用于容纳具有逻辑内容的逻辑块，包括基于逻辑设计的定时要求。 临时区域被转换为芯片上的物理单元，其中分配有针对逻辑块的输入和输出的引脚。 逻辑块以时间敏感的方式映射到芯片上的物理单元，使用定时断言来形成临时逻辑分区。 基于定时断言连接芯片上的块，包括临时逻辑分区。 在芯片上执行定时分析以确定与每个临时逻辑分区相关联的定时松弛。 确定定时松弛是否可接受。 如果时间松弛是不能接受的，则该松弛被分摊，并且分时的松弛信息以定时断言的形式被反馈。 重复映射，连接，执行定时分析和分配分配，直到确定与每个临时逻辑分区相关联的定时松弛是可接受的。

公开(公告)号：US08015426B2

公开(公告)日：2011-09-06

申请号：US12056566

申请日：2008-03-27

申请人： Dustin J. VanStee ,  Thomas J. Griffin ,  Leonard M. Greenberg

发明人： Dustin J. VanStee ,  Thomas J. Griffin ,  Leonard M. Greenberg

IPC分类号： G06F1/32

CPC分类号： G11C5/14 ,  G11C5/04

摘要： A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state of the logic circuitry. The selector enables a power source to the logic circuitry in response to the control signal indicating the active state. The selector also disables the power source to the logic circuitry in response to the control signal indicating the idle state. Thus, the power source is dynamically eliminated from the logic circuitry on the device when it is in the idle state.

摘要翻译： 一种提供电压门控的系统和方法。 该系统包括用于提供电压电源门控的装置。 该装置包括逻辑电路，用于接收与逻辑电路相关联的控制信号和选择器的机构。 控制信号指示逻辑电路的活动状态或空闲状态。 响应于指示活动状态的控制信号，该选择器使能逻辑电路的电源。 响应于指示空闲状态的控制信号，选择器还禁用逻辑电路的电源。 因此，当电源处于空闲状态时，电源在设备上的逻辑电路中被动态地消除。

公开(公告)号：US20090245008A1

公开(公告)日：2009-10-01

申请号：US12056566

申请日：2008-03-27

申请人： Dustin J. VanStee ,  Thomas J. Griffin ,  Leonard M. Greenberg

发明人： Dustin J. VanStee ,  Thomas J. Griffin ,  Leonard M. Greenberg

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C5/04

摘要： A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state of the logic circuitry. The selector enables a power source to the logic circuitry in response to the control signal indicating the active state. The selector also disables the power source to the logic circuitry in response to the control signal indicating the idle state. Thus, the power source is dynamically eliminated from the logic circuitry on the device when it is in the idle state.

摘要翻译： 一种提供电压门控的系统和方法。 该系统包括用于提供电压电源门控的装置。 该装置包括逻辑电路，用于接收与逻辑电路相关联的控制信号和选择器的机构。 控制信号指示逻辑电路的活动状态或空闲状态。 响应于指示活动状态的控制信号，该选择器使能逻辑电路的电源。 响应于指示空闲状态的控制信号，选择器还禁用逻辑电路的电源。 因此，当电源处于空闲状态时，电源在设备上的逻辑电路中被动态地消除。