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    METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MAPPING A LOGICAL DESIGN ONTO AN INTEGRATED CIRCUIT WITH SLACK APPORTIONMENT
    1.
    发明申请
    METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MAPPING A LOGICAL DESIGN ONTO AN INTEGRATED CIRCUIT WITH SLACK APPORTIONMENT 审中-公开
    方法，系统和计算机程序产品，用于将逻辑设计映射到具有滑块分配的集成电路

    公开(公告)号：US20080307374A1

    公开(公告)日：2008-12-11

    申请号：US11758277

    申请日：2007-06-05

    申请人： James C. Gregerson ,  Leonard M. Greenberg ,  Steven J. Hnatko ,  Kirk D. Lamb ,  James H. McCullen

    发明人： James C. Gregerson ,  Leonard M. Greenberg ,  Steven J. Hnatko ,  Kirk D. Lamb ,  James H. McCullen

    IPC分类号： G06F9/45

    CPC分类号： G06F17/5077 ,  G06F17/5031

    摘要： A logical design including multiple logical blocks is mapped onto an integrated circuit chip. A chip level floor plan is created on the chip, including temporary areas on the chip set aside for accommodating logical blocks having logical content including timing requirements based on the logical design. The temporary areas are translated into physical cells on the chip with pins assigned for inputs and outputs for the logical blocks. The logical blocks are mapped to the physical cells on the chip in a time sensitive manner using timing assertions to form temporary logical partitions. Blocks on the chip, including the temporary logical partitions, are connected based on the timing assertions. A timing analysis is performed on the chip to determine timing slack associated with each temporary logical partition. A determination is made whether the timing slack is acceptable. If the timing slack is not acceptable, the slack is apportioned for, and apportioned slack information is fed back in the form of timing assertions. Mapping, connecting, performing a timing analysis, and apportioning for slack are repeated until the timing slack associated with each temporary logical partition is determined to be acceptable.

    摘要翻译： 包括多个逻辑块的逻辑设计被映射到集成电路芯片上。 在芯片上创建芯片级平面图，包括芯片上的临时区域，用于容纳具有逻辑内容的逻辑块，包括基于逻辑设计的定时要求。 临时区域被转换为芯片上的物理单元，其中分配有针对逻辑块的输入和输出的引脚。 逻辑块以时间敏感的方式映射到芯片上的物理单元，使用定时断言来形成临时逻辑分区。 基于定时断言连接芯片上的块，包括临时逻辑分区。 在芯片上执行定时分析以确定与每个临时逻辑分区相关联的定时松弛。 确定定时松弛是否可接受。 如果时间松弛是不能接受的，则该松弛被分摊，并且分时的松弛信息以定时断言的形式被反馈。 重复映射，连接，执行定时分析和分配分配，直到确定与每个临时逻辑分区相关联的定时松弛是可接受的。

    Chip design and fabrication method optimized for profit
    3.
    发明授权
    Chip design and fabrication method optimized for profit 有权
    芯片设计和制造方法优化利润

    公开(公告)号：US08086988B2

    公开(公告)日：2011-12-27

    申请号：US12467326

    申请日：2009-05-18

    申请人： Nathan Buck ,  Howard H. Chen ,  James P. Eckhardt ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Susan K. Lichtensteiger ,  Chandramouli Visweswariah ,  Tad J. Wilder

    发明人： Nathan Buck ,  Howard H. Chen ,  James P. Eckhardt ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Susan K. Lichtensteiger ,  Chandramouli Visweswariah ,  Tad J. Wilder

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031

    摘要： Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.

    摘要翻译： 公开了一种计算机实现的方法，用于设计芯片以优化不同仓中的产量部分作为多个不同度量的函数，并进一步最大化所得到的芯片仓的利润潜力。 该方法分别计算联合概率分布（JPD），每个JPD是不同度量（例如，性能，功耗等）的函数。 基于JPD，生成相应的收益率曲线。 利润函数然后将所有这些度量（例如，绩效值，功耗值等）的值减小到公共利润分母（例如，指示可能与给定度量值相关联的利润的货币值）。 更具体地说，利润函数，尤其是货币价值可用于将各种收益率曲线组合成基于利润的收益率曲线，从中可以生成利润模型。 基于这种利润模型，可以对芯片设计进行改变，以便根据所有不同的指标（例如性能，功耗等）来优化产量，并进一步最大化所得芯片的利润潜力 。

    Method and system for nonsequential execution of intermixed scalar and vector instructions in a data processing system utilizing a finish instruction array
    5.
    发明授权
    Method and system for nonsequential execution of intermixed scalar and vector instructions in a data processing system utilizing a finish instruction array 失效
    在使用完成指令数组的数据处理系统中不相继执行混合标量和向量指令的方法和系统

    公开(公告)号：US5446913A

    公开(公告)日：1995-08-29

    申请号：US991665

    申请日：1992-12-16

    申请人： Norman C. Chou ,  Edward J. D'Avignon ,  James C. Gregerson ,  James R. Robinson ,  Michael S. Siegel ,  Michael A. Smoolca ,  Albert J. Van Norstrand, Jr.

    发明人： Norman C. Chou ,  Edward J. D'Avignon ,  James C. Gregerson ,  James R. Robinson ,  Michael S. Siegel ,  Michael A. Smoolca ,  Albert J. Van Norstrand, Jr.

    IPC分类号： G06F9/38 ,  G06F9/26 ,  G06F9/30

    CPC分类号： G06F9/3885 ,  G06F9/3836

    摘要： A method and system for enhancing processing efficiency in a data processing system which includes multiple scalar instruction processors and a vector instruction processor. An ordered sequence of intermixed scalar and vector instructions is processed in a nonsequential order by coupling those instructions to selected processors. As each instruction is finished an indication of that state is stored within a finish instruction array. The first vector instruction within the ordered sequence is initiated within the vector instruction processor only after an indication that each scalar instruction preceding the first vector instruction is finished. A vector advance signal is generated by the vector instruction processor each time processing of a vector instruction is initiated. A subsequent vector instruction is then initiated when the vector processor assets are available only in response to the presence of the vector advance signal and an indication that all scalar instructions which proceed the subsequent vector instruction within the ordered sequence have finished, without encountering an exception. In this manner, chained processing of vector instructions may be accomplished by initiating processing of a subsequent vector instruction only after possible interruption by a scalar instruction exception is no longer possible.

    摘要翻译： 一种用于提高包括多个标量指令处理器和向量指令处理器的数据处理系统中的处理效率的方法和系统。 通过将这些指令耦合到所选择的处理器，以非顺序的顺序处理混合标量和向量指令的有序序列。 当每个指令完成时，该状态的指示被存储在完成指令数组中。 只有在第一个向量指令之前的每个标量指令完成的指示之后，才能在向量指令处理器内启动有序序列内的第一个向量指令。 每次向量指令的处理开始时，矢量提前信号由矢量指令处理器产生。 然后，当向量处理器资产仅在响应于向量提前信号的存在而可用时才启动随后的向量指令，并且指示在序列序列中进行随后的向量指令的所有标量指令已经完成，而不会遇到异常。 以这种方式，可以通过仅在通过标量指令异常的可能中断之后启动对后续向量指令的处理来实现向量指令的链接处理。

    CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT
    7.
    发明申请
    CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT 有权
    芯片设计和优化方法优化

    公开(公告)号：US20100293512A1

    公开(公告)日：2010-11-18

    申请号：US12467326

    申请日：2009-05-18

    申请人： Nathan Buck ,  Howard H. Chen ,  James P. Eckhardt ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Susan K. Lichtensteiger ,  Chandramouli Visweswariah ,  Tad J. Wilder

    发明人： Nathan Buck ,  Howard H. Chen ,  James P. Eckhardt ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Susan K. Lichtensteiger ,  Chandramouli Visweswariah ,  Tad J. Wilder

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031

    摘要： Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.

    摘要翻译： 公开了一种计算机实现的方法，用于设计芯片以优化不同仓中的产量部分作为多个不同度量的函数，并进一步最大化所得到的芯片仓的利润潜力。 该方法分别计算联合概率分布（JPD），每个JPD是不同度量（例如，性能，功耗等）的函数。 基于JPD，生成相应的收益率曲线。 利润函数然后将所有这些度量（例如，绩效值，功耗值等）的值减小到公共利润分母（例如，指示可能与给定度量值相关联的利润的货币值）。 更具体地说，利润函数，尤其是货币价值可用于将各种收益率曲线组合成基于利润的收益率曲线，从中可以产生利润模型。 基于这种利润模型，可以对芯片设计进行改变，以便根据所有不同的指标（例如性能，功耗等）来优化产量，并进一步最大化所得芯片的利润潜力 。

    METHOD, COMPUTER PROGRAM PRODUCT, AND APPARATUS FOR STATIC TIMING WITH RUN-TIME REDUCTION
    9.
    发明申请
    METHOD, COMPUTER PROGRAM PRODUCT, AND APPARATUS FOR STATIC TIMING WITH RUN-TIME REDUCTION 失效
    方法，计算机程序产品和运行时间减少的静态时序设备

    公开(公告)号：US20080163147A1

    公开(公告)日：2008-07-03

    申请号：US11619349

    申请日：2007-01-03

    申请人： James C. Gregerson ,  Kerim Kalafala ,  Alexander Suess

    发明人： James C. Gregerson ,  Kerim Kalafala ,  Alexander Suess

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： Run-time reduction is achieved in timing performance of a logical design, such as a digital integrated circuit. A portion of the logical design that is expected to be stable with respect to timing performance, such as a clock tree, is identified. Timing sensitivities, including sensitivities to sources of variability, of the identified portion of the logical design are determined at a given instant. The timing sensitivities of the identified portion of the logical design are saved for re-use. The saved timing sensitivities are re-used throughout the timing analysis and in subsequent timing analyses.

    摘要翻译： 在诸如数字集成电路之类的逻辑设计的时序性能上实现了运行时间的减少。 识别期望相对于定时性能稳定的逻辑设计的一部分，例如时钟树。 在给定的时刻确定逻辑设计的识别部分的时间灵敏度，包括对变异源的敏感性。 逻辑设计的识别部分的定时灵敏度被保存以供重新使用。 保存的定时灵敏度在整个时序分析和随后的时序分析中被重新使用。