公开(公告)号：US4962497A

公开(公告)日：1990-10-09

申请号：US410774

申请日：1989-09-21

Applicant: James J. Ferenc ,  Louis R. Goke ,  Gary J. Grimes ,  Bryan S. Moffitt

Inventor： James J. Ferenc ,  Louis R. Goke ,  Gary J. Grimes ,  Bryan S. Moffitt

IPC: H04L12/64 ,  H04Q11/04

CPC classification number: H04L12/64 ,  H04Q11/0407

Abstract: A modular, substantially infinitely-growable, multi-node switching system operates under distributed control to serve integrated circuit-switched and packet-switched traffic at the data rates appropriate for each type of traffic. The system comprises a plurality of interconnected identical switching units that form at least one communication switching node. A communication switching node is a modular building block of the system; a switching unit is a modular building block of a switching node, and hence also of the system. A plurality of communication endpoint nodes--illustratively PBXs--is connected to the one or more switching nodes for communicating with each other through the switching nodes. A plurality of communication links each connect a different one of the system's switching units to either (a) one of the communication endpoint nodes or (b) a unit of another switching node. All of the links have the same communication format. Each switching node includes a plurality of different ones of the identical switching units, and a communication medium that interconnects all of the units of the switching node to allow each unit of a node to broadcast all communications received from a connected link to all of the units of the node.

Abstract translation: 模块化的，基本上无限可生长的多节点交换系统在分布式控制下操作，以适合于每种类型业务的数据速率来服务集成电路交换和分组交换业务。 该系统包括形成至少一个通信交换节点的多个互连的相同的交换单元。 通信交换节点是系统的模块化构建块; 切换单元是交换节点的模块化构建块，并且因此也是系统的模块化构建块。 多个通信端点节点（例如PBX）连接到一个或多个交换节点，用于通过交换节点彼此通信。 多个通信链路各自将系统的交换单元中的不同的一个连接到（a）通信端点节点之一或（b）另一个交换节点的单元。 所有链接都具有相同的通信格式。 每个交换节点包括多个不同的相同交换单元，以及通信介质，其互连交换节点的所有单元，以允许节点的每个单元将从连接的链路接收的所有通信广播到所有单元 的节点。

公开(公告)号：US4592044A

公开(公告)日：1986-05-27

申请号：US613049

申请日：1984-05-22

Applicant: James J. Ferenc

Inventor： James J. Ferenc

IPC: H04J3/14 ,  H04L1/24 ,  H04M3/24 ,  H04Q11/04 ,  H04J1/16 ,  G06F7/34 ,  H04B3/46

CPC classification number: H04Q11/04 ,  H04J3/14 ,  H04L1/241 ,  H04L1/243 ,  H04M3/244

Abstract: Apparatus and method are disclosed for checking the time slot data word integrity of data communications in a time multiplexed communication system. A predetermined control bit of each data word of a data frame is alternately switched from its normal control bit function to a bit of a pseudo random sequence (PRS) for time slot data word integrity checking. During alternate data frames a checking circuit compares the predetermined bit of received consecutive data words against consecutive bits of a reference PRS and outputs a time slot cross connect error signal when a difference occurs.

Abstract translation: 公开了用于检查时分复用通信系统中数据通信的时隙数据字完整性的装置和方法。 将数据帧的每个数据字的预定控制位从其正常控制位功能交替地切换到用于时隙数据字完整性检查的伪随机序列（PRS）的位。 在替代数据帧期间，检查电路将接收到的连续数据字的预定位与参考PRS的连续位进行比较，并且当发生差异时输出时隙交叉错误信号。

公开(公告)号：US4731785A

公开(公告)日：1988-03-15

申请号：US876613

申请日：1986-06-20

Applicant: James J. Ferenc ,  Robert W. Gebhardt ,  Gary J. Grimes ,  Edward B. Morgan, Jr. ,  Gabe A. Sellers, III

Inventor： James J. Ferenc ,  Robert W. Gebhardt ,  Gary J. Grimes ,  Edward B. Morgan, Jr. ,  Gabe A. Sellers, III

IPC: H04Q11/04 ,  H04J3/16 ,  H04L12/64 ,  H04J3/02 ,  H04J3/24

CPC classification number: H04J3/1682

Abstract: Apparatus for and a method of inserting circuit switch information and packetized data into different time slots of a time division multiplexed bus. A memory having a location individual to each time slot is written with information specifying whether the time slot individual to each location is to serve circuit switch information or packet data. The readout of each memory location during the occurrence of it's associated time slot controllably effects the application of either the circuit switch information or the packet data to the bus. Packet data can be inserted into each time slot not currently being used by the circuit switch. A special information bit is inserted into each time slot to specify whether the remainder of the bits of the time slot represents circuit switch or packet information. The information bit is used by receiving apparatus to steer the bits of each time slot to either a receiving circuit switch or a receiving packet switch.

Abstract translation: 将电路交换信息和分组数据插入到时分复用总线的不同时隙中的装置和方法。 具有每个时隙独立的位置的存储器被写入具有指定每个位置的个别时隙是否用于电路交换信息或分组数据的信息。 每个存储器位置在其相关时隙发生期间的读出可控地影响电路交换机信息或分组数据到总线的应用。 分组数据可以插入电路交换机当前未使用的每个时隙。 每个时隙中插入一个特殊信息位，以指定该时隙的剩余位是否表示电路交换机或分组信息。 信息位由接收装置用于将每个时隙的比特转向接收电路交换机或接收分组交换机。