-
1.发明授权Data processing system for generating symmetrical range of addresses of instructing-address-value with the use of inverting sign value 失效数据处理系统，用于使用反转符号值产生指令地址值的对称地址范围
公开(公告)号：US5386534A
公开(公告)日：1995-01-31
申请号：US967295
申请日：1992-10-27
CPC分类号： G06F7/505 , G06F9/322 , G06F9/355 , G06F2207/3832
摘要： A data processing system (10) performs indexed addressing, autoincrementing, and autodecrementing using power of two byte boundaries. For example, a 5-bit offset allows a user to progress sixteen bytes either forward or backward through a table of data. An instruction specifying an operation to be performed, a pointer register (58, 60), and an offset value is provided to an execution unit (14). The pointer register (58, 60) stores a first address value and the offset value has a sign and a magnitude. An arithmetic logic unit, ALU, (52) inverts the sign of the offset value to provide an inverted sign value. A plurality of adders (100, 102, 104, 106, and 108) adds the offset value, the first address value, and the inverted sign value to generate an offset sum. A positive offset value is increased by one to generate a symmetric power of two offset range.
摘要翻译： 数据处理系统（10）使用两个字节边界的功率来执行索引寻址，自动增量和自动递减。 例如，5位偏移允许用户通过数据表向前或向后前进16个字节。 指定要执行的操作的指令，指针寄存器（58,60）和偏移值被提供给执行单元（14）。 指针寄存器（58,60）存储第一地址值，并且偏移值具有符号和幅度。 算术逻辑单元ALU（52）使偏移值的符号反转以提供反相符号值。 多个加法器（100,102,104,106和108）将偏移值，第一地址值和反转符号值相加以产生偏移和。 正偏移值增加1以产生两个偏移范围的对称功率。
-
2.发明授权Circuit and method for determining membership in a set during a fuzzy logic operation 失效用于在模糊逻辑运算期间确定集合中的隶属度的电路和方法
公开(公告)号：US5295229A
公开(公告)日：1994-03-15
申请号：US899975
申请日：1992-06-17
CPC分类号： G06N7/04 , Y10S706/90
摘要： A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. An operand assignment circuit (50) and an ALU (56) allow circuit (14) to determine the degree of membership more quickly. Assignment circuit (50) determines a multiplier for a multiplication operation based on a number of significant bits in the values to be multiplied. If the multiplier is smaller than the multiplicand, shorter multiplication operations may be performed. Additionally, ALU (56) operates in a split mode of operation which is able to perform two eight bit subtraction or multiplication operations concurrently which also results in these operations being performed more efficiently.
摘要翻译： 一种在模糊逻辑运算期间确定隶属集中的输入的隶属程度的电路（14）和方法。 隶属度由单一的“MEM”软件指令计算。 MEM指令确定系统输入是否具有零度，饱和度级别或其间的一些值的隶属度。 操作数分配电路（50）和ALU（56）允许电路（14）更快地确定隶属度。 分配电路（50）基于要乘以的值中的有效位数来确定乘法运算的乘数。 如果乘法器小于被乘数，则可以执行较短的乘法运算。 此外，ALU（56）以分割操作模式操作，其能够同时执行两个8位减法或乘法运算，这也导致这些操作更有效地执行。
-
公开(公告)号：US5263125A
公开(公告)日：1993-11-16
申请号：US899968
申请日：1992-06-17
CPC分类号： G06N7/04 , Y10S706/90
摘要： A circuit (14) to evaluate a plurality of fuzzy logic rules in a data processor (10) in response to a single "REV" software instruction. The REV instruction evaluates the rules stored in a memory (32) to determine a rule strength of each. Antecedents are separated from consequences of each of the rules by a buffer address. To evaluate the antecedents, an ALU (52) subtracts an antecedent in memory (32) from a current antecedent stored in an accumulator (58). Subsequently, a swap logic (46) provides control information to assign a minimum value as a rule strength of the rule. Similarly, a maximum rule strength is required during evaluation of the consequences. ALU (52) subtracts a consequence in memory (32) from a consequence stored in accumulator (58). Depending on a result, swap logic (46) provides control information to assign a maximum rule strength to the consequences of the evaluated rule.
-
4.发明授权Circuit and method for determining membership in a set during a fuzzy logic operation 失效用于在模糊逻辑运算期间确定集合中的隶属度的电路和方法
公开(公告)号：US5805774A
公开(公告)日：1998-09-08
申请号：US853660
申请日：1997-05-09
申请人： J. Greg Viot , James M. Sibigtroth
发明人： J. Greg Viot , James M. Sibigtroth
CPC分类号： G06N7/04 , Y10S706/90
摘要： A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. If a membership function has a boundary with an infinite slope, the slope value is set equal to zero and the degree of membership is then set equal to a saturation value for those input values corresponding to the infinite slope boundary.
摘要翻译： 一种在模糊逻辑运算期间确定隶属集中的输入的隶属程度的电路（14）和方法。 隶属度由单一的“MEM”软件指令计算。 MEM指令确定系统输入是否具有零度，饱和度级别或其间的一些值的隶属度。 如果隶属函数具有无限斜率的边界，则将斜率值设置为等于零，然后将隶属度设置为等于对应于无限斜率边界的那些输入值的饱和值。
-
公开(公告)号：US5119325A
公开(公告)日：1992-06-02
申请号：US622029
申请日：1990-12-04
申请人： J. Greg Viot , James L. Broseghini , Eytan Hartung , John P. Dunn
发明人： J. Greg Viot , James L. Broseghini , Eytan Hartung , John P. Dunn
IPC分类号： G06F7/52
CPC分类号： G06F7/5338
摘要： An adder circuit that has an encoded carry input, where a bit position weight of the carry input is two, allows the adder circuit to selectively concurrently add a data value of two to a first and a second input data operand of the adder circuit. The adder circuit is also able to add the first and second input data operands with a second carry input that is not encoded. A recoded multiplier combines two partial product calculations into one calculation during only a first partial product calculation operation by using the adder circuit. Partial product calculations are reduced in number during a multiply operation of a data processor.
摘要翻译： 具有编码进位输入的加法器电路，其中进位输入的位位置权重为2，允许加法器电路选择性地将二值的数据值添加到加法器电路的第一和第二输入数据操作数。 加法器电路还能够用不被编码的第二进位输入来添加第一和第二输入数据操作数。 重新编码的乘法器通过使用加法器电路在仅第一部分乘积计算操作期间将两个部分乘积计算结合成一个计算。 在数据处理器的乘法运算期间，部分产品计算数量减少。
-
公开(公告)号：US5051943A
公开(公告)日：1991-09-24
申请号：US622078
申请日：1990-12-04
申请人： J. Greg Viot , James L. Broseghini , Eytan Hartung , John P. Dunn
发明人： J. Greg Viot , James L. Broseghini , Eytan Hartung , John P. Dunn
CPC分类号： G06F7/5336 , G06F7/501
摘要： An adder circuit that has an encoded carry input, where a bit position weight of the carry input is two, allows the adder circuit to selectively concurrently add a data value of two to a first and a second input data operand of the adder circuit. The adder circuit is also able to add the first and second input data operands with a second carry input that is not encoded. A recoded multiplier combines two partial product calculations into one calculation during only a first partial product calculation operation by using the adder circuit. Partial product calculations are reduced in number during a multiply operation of a data processor.
摘要翻译： 具有编码进位输入的加法器电路，其中进位输入的位位置权重为2，允许加法器电路选择性地将二值的数据值加到加法器电路的第一和第二输入数据操作数。 加法器电路还能够用不被编码的第二进位输入来添加第一和第二输入数据操作数。 重新编码的乘法器通过使用加法器电路在仅第一部分乘积计算操作期间将两个部分乘积计算结合成一个计算。 在数据处理器的乘法运算期间，部分产品计算数量减少。
-
公开(公告)号：US5684928A
公开(公告)日：1997-11-04
申请号：US570454
申请日：1995-12-11
申请人： J. Greg Viot , James M. Sibigtroth
发明人： J. Greg Viot , James M. Sibigtroth
CPC分类号： G06N7/04 , Y10S706/90
摘要： In a data processing system (10) implementing a fuzzy logic operation, a switching mechanism (802) is implemented to provide a selection between a variable format rule base (803) and a fixed format rule base. The variable format rule base utilizes buffers between fuzzy input addresses and fuzzy output addresses, while the fixed format rule base does not require such buffers since a number of fuzzy input addresses and fuzzy output addresses is predetermined.
摘要翻译： 在实现模糊逻辑运算的数据处理系统（10）中，实现切换机制（802）以提供可变格式规则库（803）和固定格式规则库之间的选择。 可变格式规则库利用模糊输入地址和模糊输出地址之间的缓冲器，而固定格式规则库不需要这种缓冲器，因为预定了多个模糊输入地址和模糊输出地址。
-
公开(公告)号：US5737493A
公开(公告)日：1998-04-07
申请号：US570453
申请日：1995-12-11
CPC分类号： G06N7/04 , Y10S706/90
摘要： A circuit (14) to evaluate a plurality of fuzzy logic rules as executable instructions in a data processor (310). A first instruction retrieves a fuzzy input value from memory (32) and stores it in an accumulator (58). A second instruction retrieves a second fuzzy input value from memory (32) and compares it to the fuzzy input value stored in the accumulator (58). The minimum value of the two fuzzy input values is then allowed to remain in the accumulator (58). Another program instruction retrieves a fuzzy output value from memory (32) and compares it to the value in the accumulator (58). The maximum of these two values is then determined by the instruction and this maximum value is then stored in memory (32).
摘要翻译： 一种用于评估多个模糊逻辑规则作为数据处理器（310）中的可执行指令的电路（14）。 第一指令从存储器（32）检索模糊输入值并将其存储在累加器（58）中。 第二指令从存储器（32）检索第二模糊输入值，并将其与存储在累加器（58）中的模糊输入值进行比较。 然后允许两个模糊输入值的最小值保留在累加器（58）中。 另一个程序指令从存储器（32）检索模糊输出值，并将其与累加器（58）中的值进行比较。 然后由指令确定这两个值的最大值，然后将该最大值存储在存储器（32）中。
-
9.发明授权Circuit and method for determining membership in a set during a fuzzy logic operation 失效用于在模糊逻辑运算期间确定集合中的隶属度的电路和方法
公开(公告)号：US5687289A
公开(公告)日：1997-11-11
申请号：US357468
申请日：1994-12-16
申请人： J. Greg Viot , James M. Sibigtroth
发明人： J. Greg Viot , James M. Sibigtroth
CPC分类号： G06N7/04 , Y10S706/90
摘要： A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. If a membership function has a boundary with an infinite slope, the slope value is set equal to zero and the degree of membership is then set equal to a saturation value for those input values corresponding to the infinite slope boundary.
摘要翻译： 一种在模糊逻辑运算期间确定隶属集中的输入的隶属程度的电路（14）和方法。 隶属度由单一的“MEM”软件指令计算。 MEM指令确定系统输入是否具有零度，饱和度级别或其间的一些值的隶属度。 如果隶属函数具有无限斜率的边界，则将斜率值设置为等于零，然后将隶属度设置为等于对应于无限斜率边界的那些输入值的饱和值。
-
10.发明授权Data processing system for resuming instruction execution after an interrupt and method therefor 失效用于在中断后恢复指令执行的数据处理系统及其方法
公开(公告)号：US5475822A
公开(公告)日：1995-12-12
申请号：US151635
申请日：1993-11-15
CPC分类号： G06F9/3001 , G06F9/325 , G06F9/3861
摘要： The data processing system(10) implements a resumable instruction using two instruction bytes. When a program counter (72) points to a first instruction byte, a first data processing operation is initiated. If an interrupt occurs during execution of the first data processing operation, intermediate data calculations held in a plurality of temporary registers (64, 66, 68) are saved in stack memory at a location pointed to by the stack pointer register (72). The program counter is incremented to point to a second byte of the instruction. An instruction resume operation is executed and the intermediate results of the data processing operation are accessed from the stack memory and restored to respective storage locations within the data processing system. After the intermediate results are restored, the program counter is decremented to point to the first instruction byte and the instruction continues executing the data processing operation as though no interrupt occurred.
摘要翻译： 数据处理系统（10）使用两个指令字节实现可恢复指令。 当程序计数器（72）指向第一指令字节时，启动第一数据处理操作。 如果在执行第一数据处理操作期间发生中断，则将保存在多个临时寄存器（64,66,68）中的中间数据计算保存在由堆栈指针寄存器（72）指向的位置的堆栈存储器中。 程序计数器递增到指令的第二个字节。 执行指令恢复操作，并且从堆栈存储器访问数据处理操作的中间结果，并恢复到数据处理系统内的相应存储位置。 在中间结果恢复之后，程序计数器递减到指向第一指令字节，并且指令继续执行数据处理操作，就好像没有中断发生一样。
-
-
-
-
-
-
-
-
-
搜索结果
16 条记录 (耗时 0.023 秒)