公开(公告)号：US06760245B2

公开(公告)日：2004-07-06

申请号：US10138076

申请日：2002-05-01

申请人： James R. Eaton, Jr. ,  Philip John Kuekes

发明人： James R. Eaton, Jr. ,  Philip John Kuekes

IPC分类号： G11C1700

CPC分类号： G11C13/003 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0023 ,  G11C2213/75 ,  G11C2213/77 ,  G11C2213/81 ,  H01L27/285 ,  H01L51/0052 ,  H01L51/0595 ,  Y10S977/943

摘要： A nano-scale flash memory comprises: (a) source and drain regions in a plurality of approximately parallel first wires, the first wires comprising a semiconductor material, the source and drain regions separated by a channel region; (b) gate electrodes in a plurality of approximately parallel second wires, the second wires comprising either a semiconductor material or a metal, the second wires crossing the first wires at a non-zero angle over the channel regions, to form an array of nanoscale transistors; and (c) a hot electron trap region at each intersection of the first wires with the second wires. Additionally, crossed-wire transistors are provided that can either form a configurable transistor or a switch memory bit that is capable of being set by application of a voltage. The crossed-wire transistors can be formed in a crossbar array.

摘要翻译： 纳米级闪速存储器包括：（a）多个大致平行的第一布线中的源极和漏极区域，所述第一布线包括半导体材料，所述源极和漏极区域被沟道区域分开; （b）多个大致平行的第二导线中的栅电极，第二导线包括半导体材料或金属，第二导线在沟道区域上以非零角度穿过第一导线，以形成纳米级阵列 晶体管 和（c）第一导线与第二导线的每个交叉处的热电子陷阱区。 此外，提供了可以形成可配置晶体管或能够通过施加电压来设置的开关存储器位的交叉线晶体管。 交叉线晶体管可以形成在横杆阵列中。