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公开(公告)号：US06760245B2
公开(公告)日：2004-07-06
申请号：US10138076
申请日：2002-05-01
IPC分类号： G11C1700
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/0014 , G11C13/0023 , G11C2213/75 , G11C2213/77 , G11C2213/81 , H01L27/285 , H01L51/0052 , H01L51/0595 , Y10S977/943
摘要： A nano-scale flash memory comprises: (a) source and drain regions in a plurality of approximately parallel first wires, the first wires comprising a semiconductor material, the source and drain regions separated by a channel region; (b) gate electrodes in a plurality of approximately parallel second wires, the second wires comprising either a semiconductor material or a metal, the second wires crossing the first wires at a non-zero angle over the channel regions, to form an array of nanoscale transistors; and (c) a hot electron trap region at each intersection of the first wires with the second wires. Additionally, crossed-wire transistors are provided that can either form a configurable transistor or a switch memory bit that is capable of being set by application of a voltage. The crossed-wire transistors can be formed in a crossbar array.
摘要翻译： 纳米级闪速存储器包括：（a）多个大致平行的第一布线中的源极和漏极区域，所述第一布线包括半导体材料，所述源极和漏极区域被沟道区域分开; （b）多个大致平行的第二导线中的栅电极，第二导线包括半导体材料或金属，第二导线在沟道区域上以非零角度穿过第一导线，以形成纳米级阵列 晶体管 和（c）第一导线与第二导线的每个交叉处的热电子陷阱区。 此外，提供了可以形成可配置晶体管或能够通过施加电压来设置的开关存储器位的交叉线晶体管。 交叉线晶体管可以形成在横杆阵列中。
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公开(公告)号：US06927996B2
公开(公告)日：2005-08-09
申请号：US10676465
申请日：2003-09-30
IPC分类号： G11C11/15 , G11C7/00 , G11C7/12 , G11C11/14 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08
摘要： A magnetic random access memory (MRAM) includes an array of magnetic memory cells arranged on a cross-point grid. Spurious voltages that build up on the stray wiring capacitance of unselected bit and word select lines are limited and discharged by diodes. The control of such spurious voltages improves device operating margins and allows the construction of larger arrays.
摘要翻译： 磁性随机存取存储器（MRAM）包括布置在交叉点网格上的磁存储器单元的阵列。 在未选择位和字选择线的杂散布线电容上形成的杂散电压受到二极管的限制和放电。 这种杂散电压的控制提高了器件工作裕度，并允许构建更大的阵列。
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3.发明授权System for and method of four-conductor magnetic random access memory cell and decoding scheme 有权四导体磁性随机存取存储单元和解码方案的系统和方法公开(公告)号：US06842389B2
公开(公告)日：2005-01-11
申请号：US10346700
申请日：2003-01-17
IPC分类号： G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C7/02 , G11C7/00
CPC分类号： G11C11/16
摘要： A four-conductor MRAM device comprising an array of memory cells, each of the memory cells including a first magnetic layer, a dielectric, and a second magnetic layer; a plurality of local column sense lines wherein one is electrically connected to the first magnetic layer of the array of memory cells; a plurality of local row sense lines wherein one of the local row sense lines is electrically connected to the second magnetic layer of the array of memory cells; a plurality of global column write lines parallel to the plurality of local column sense lines; a plurality of global row write lines parallel to the plurality of local row sense lines; and wherein the plurality of local column sense lines and the plurality of local row sense lines are connected to read data from the array of memory cells and the plurality of global column write lines and the plurality of global row write lines are connected to write data to the array of memory cells.
摘要翻译： 一种包括存储器单元阵列的四导体MRAM器件，每个存储器单元包括第一磁性层，电介质和第二磁性层; 多个局部列感测线，其中一个电连接到存储器单元阵列的第一磁性层; 多个局部行感测线，其中本地行读出线之一电连接到存储器单元阵列的第二磁性层; 平行于所述多个局部列感测线的多个全局列写入线; 平行于多个局部行感测线的多个全局行写行; 并且其中所述多个局部列感测线和所述多个本地行读传感线被连接以从所述存储器单元阵列读取数据，并且所述多个全局列写行和所述多个全局行写行被连接以将数据写入 存储单元阵列。
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公开(公告)号：US07376004B2
公开(公告)日：2008-05-20
申请号：US10661448
申请日：2003-09-11
CPC分类号： G11C11/16
摘要： A method for making magnetic random access memories (MRAM) isolates each and every memory cell in an MRAM array during operation until selected. Some embodiments use series connected diodes for such electrical isolation. Only a selected one of the memory cells will then conduct current between respective ones of the bit and word lines. A better, more uniform distribution of read and data-write data access currents results to all the memory cells. In another embodiment, this improvement is used to increase the number of rows and columns to support a larger data array. In a further embodiment, such improvement is used to increase operating margins and reduce necessary data-write voltages and currents.
摘要翻译： 用于制造磁随机存取存储器（MRAM）的方法在操作期间隔离MRAM阵列中的每个存储单元直到被选择。 一些实施例使用用于这种电隔离的串联连接的二极管。 只有选定的一个存储器单元将在相应的位和字线之间传导电流。 读取和写入数据访问电流的更好，更均匀的分布会导致所有存储单元。 在另一个实施例中，该改进用于增加支持较大数据阵列的行数和列数。 在另一实施例中，这种改进用于增加操作裕度并减少必要的数据写入电压和电流。
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公开(公告)号：US06864529B2
公开(公告)日：2005-03-08
申请号：US09934548
申请日：2001-08-23
申请人： Ping Mei , James R. Eaton, Jr.
发明人： Ping Mei , James R. Eaton, Jr.
IPC分类号： G11C16/04 , G11C5/06 , G11C16/02 , G11C17/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C17/16
摘要： A memory device includes a memory array of thin film transistor (TFT) memory cells. The memory cells include a floating gate separated from a gate electrode portion of a gate line by an insulator. The gate electrode portion includes a diffusive conductor that diffuses through the insulator under the application of a write voltage. The diffusive conductor forms a conductive path through the insulator that couples the gate line to the floating gate, changing the gate capacitance and therefore the state of the memory cell. The states of the memory cells are detectable as the differing current values for the memory cells. The memory cells are three terminal devices, and read currents do not pass through the conductive paths in the memory cells during read operations. This renders the memory cells robust, because read currents will not interfere with the storage mechanism in the memory cells. The memory array can be fabricated using multiple steps using the same mask. The use of a single mask for multiple steps reduces the time and cost involved in fabricating the memory array.
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6.发明授权公开(公告)号：US06781918B1
公开(公告)日：2004-08-24
申请号：US10777000
申请日：2004-02-10
IPC分类号： G11C800
CPC分类号： G11C8/12
摘要： An electrically addressable data storage unit has a matrix of rows and columns of data storage arrays on a single substrate. Each array is a matrix of coplanar data storage diode cells connected by row lines and column lines for recording, addressing and reading of data. Address lines and power lines of each array are connected to the array so that only the data storage diode cells of a selected data storage cell are enabled, thereby eliminating undesirable power dissipation in all other arrays of the array. A controller enables the row and column address lines to selectively address a diode cell in a selected array.
摘要翻译： 电可寻址数据存储单元在单个基板上具有数据存储阵列的行和列的矩阵。 每个阵列是通过行线和列线连接的共平面数据存储二极管单元的矩阵，用于记录，寻址和读取数据。 每个阵列的地址线和电源线连接到阵列，使得只有所选择的数据存储单元的数据存储二极管单元被使能，从而消除阵列的所有其它阵列中的不期望的功率耗散。 控制器使得行和列地址线能够选择性地寻址所选阵列中的二极管单元。
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公开(公告)号：US06738307B2
公开(公告)日：2004-05-18
申请号：US10145337
申请日：2002-05-13
IPC分类号： G11C800
CPC分类号： G11C8/12
摘要： An electrically addressable data storage unit has a matrix of rows and columns of data storage arrays on a single substrate. Each array is a matrix of coplanar data storage diode cells connected by row lines and column lines for recording, addressing and reading of data. Address lines and power lines of each array are connected to the array so that only the data storage diode cells of a selected data storage cell are enabled, thereby eliminating undesirable power dissipation in all other arrays of the array. A controller enables the row and column address lines to selectively address a diode cell in a selected array.
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公开(公告)号：US06501697B1
公开(公告)日：2002-12-31
申请号：US09976304
申请日：2001-10-11
IPC分类号： G11C702
CPC分类号： G11C7/062 , G11C7/06 , G11C11/16 , G11C11/56 , G11C11/5607 , G11C2207/063
摘要： A sense amplifier is provided for reading data in a multiple-state memory cell of a resistive memory array in response to a read voltage applied across the sensed memory cell, including a differential amplifier having first and second input nodes. A sense circuit determines the current in the memory cell with the read voltage applied thereto and applies a sense current representative of the memory cell current to the first input node of the differential amplifier. A reference circuit has first and second resistive elements for applying a reference current to the second input node of the differential amplifier to provide a reference value against which to compare the sense current to determine the state of the memory cell. The first resistive element has a resistance representative of a first state of the memory cell, and the second resistive element has a resistance representative of a second state of the memory cell. A voltage source for applying the read voltage across the first and second resistive elements to generate a reference current by averaging the currents through the first and second resistive elements. A first translator transistor applies the sense current to the first node of the differential amplifier. A second translator transistor applies the reference current to the second node of the differential amplifier. A comparator circuit is used to compare the signals at the first and second input nodes of the differential amplifier to provide an output indicative of the state of the sensed memory cell.
摘要翻译： 提供读出放大器，用于响应于在感测到的存储单元上施加的读取电压来读取电阻存储器阵列的多状态存储单元中的数据，包括具有第一和第二输入节点的差分放大器。 感测电路以施加读取电压的方式确定存储单元中的电流，并将表示存储单元电流的感测电流施加到差分放大器的第一输入节点。 参考电路具有第一和第二电阻元件，用于将参考电流施加到差分放大器的第二输入节点，以提供参考值，用于比较感测电流以确定存储器单元的状态。 第一电阻元件具有表示存储单元的第一状态的电阻，并且第二电阻元件具有表示存储单元的第二状态的电阻。 电压源，用于通过对通过第一和第二电阻元件的电流进行平均来施加跨越第一和第二电阻元件的读取电压以产生参考电流。 第一转换晶体管将感测电流施加到差分放大器的第一节点。 第二转换晶体管将参考电流施加到差分放大器的第二节点。 比较器电路用于比较差分放大器的第一和第二输入节点处的信号，以提供指示感测的存储器单元的状态的输出。
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9.发明授权System for and method of accessing a four-conductor magnetic random access memory 有权访问四导体磁性随机存取存储器的系统和方法公开(公告)号：US06839270B2
公开(公告)日：2005-01-04
申请号：US10346494
申请日：2003-01-17
CPC分类号： G11C11/16
摘要： A control circuit for writing to and reading from MRAMs comprising a row decoder; a first read/write row driver connected to the row decoder; a plurality of global row write conductors connected to the first read/write row driver; a plurality of row taps connected to each of the global row write conductors; and a second read/write row driver connected to the global row write conductors.
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公开(公告)号：US06661704B2
公开(公告)日：2003-12-09
申请号：US10006723
申请日：2001-12-10
申请人： James R. Eaton, Jr.
发明人： James R. Eaton, Jr.
IPC分类号： G11C1714
摘要： A method of and apparatus for connecting the sense current line in a cross-point memory array greatly reduces the effect of reverse leakage from unaddressed row or column lines. Separate sense line segments are coupled to separate stripes of row or column lines. Each sense line segment is connected to a sense diode, and each sense diode is connected to a sense bus. Each sense diode provides the current path for sensing on a selected row or column line, while allowing the leakage of only one diode per sense line segment for the unaddressed row or column lines. This arrangement results in wider margins for sensing the state of data cells in a cross-point memory array and simpler circuitry design for the memory array.
摘要翻译： 用于在交叉点存储器阵列中连接感测电流线的方法和装置大大降低了来自非寻址行或列线的反向泄漏的影响。 单独的感测线段耦合到行或列线的分隔条纹。 每个感测线段连接到感测二极管，并且每个感测二极管连接到感测总线。 每个感测二极管提供用于在所选行或列线上感测的电流路径，同时允许仅针对非寻址行或列线的每个感测线段仅泄漏一个二极管。 这种布置导致用于感测交叉点存储器阵列中的数据单元的状态和用于存储器阵列的更简单的电路设计的更大的余量。
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