利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.039 秒)

    Lookup table addressing system and method
    6.
    发明授权
    Lookup table addressing system and method 有权
    查找表寻址系统和方法

    公开(公告)号：US08285972B2

    公开(公告)日：2012-10-09

    申请号：US11258662

    申请日：2005-10-26

    申请人： James Wilson ,  Joshua A. Kablotsky ,  Yosef Stein ,  Christopher M. Mayer

    发明人： James Wilson ,  Joshua A. Kablotsky ,  Yosef Stein ,  Christopher M. Mayer

    IPC分类号： G06F9/34

    CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/345 ,  G06F9/3552 ,  G09C1/00 ,  H04L9/06 ,  H04L2209/122

    摘要： Lookup table addressing of a set of lookup tables in an external memory is achieved by: transferring a data word from a compute unit to an input register in a data address generator; providing in at least one deposit-increment index register in the data address generator including a table base field for identifying the location of the set of tables in memory, and a displacement field; and depositing a section of the data word into a displacement field in the index register for identifying the location of a specific entry in the tables.

    摘要翻译： 通过以下方式实现外部存储器中的一组查找表的查找表寻址：将数据字从计算单元传送到数据地址生成器中的输入寄存器; 在数据地址生成器中的至少一个存储增量索引寄存器中提供包括用于识别存储器中的一组表的位置的表基字段和位移字段; 以及将所述数据字的一部分存储在所述索引寄存器中的位移字段中，以用于识别所述表中的特定条目的位置。

    Programmable compute system for executing an H.264 binary decode symbol instruction
    7.
    发明授权
    Programmable compute system for executing an H.264 binary decode symbol instruction 有权
    用于执行H.264二进制解码符号指令的可编程计算系统

    公开(公告)号：US07498960B2

    公开(公告)日：2009-03-03

    申请号：US11788094

    申请日：2007-04-19

    申请人： James Wilson ,  Joshua A. Kablotsky ,  Yosef Stein ,  Christopher M. Mayer

    发明人： James Wilson ,  Joshua A. Kablotsky ,  Yosef Stein ,  Christopher M. Mayer

    IPC分类号： H03M7/00

    CPC分类号： H03M7/4006

    摘要： A compute system for executing an h.264 binary decode symbol instruction including a first compute unit having a range normalization circuit and an rLPS update circuit, and operating in a first mode responsive to current rLPS, range, value and current context to generate the next normalized range and next rLPS for the current context; a second compute unit including a value update circuit, a context update circuit, and value normalization circuit responsive to current rLPS, range value and current context to obtain the output bit, normalized value and the updated current context; and a third compute unit or said first compute unit operating in a second mode including a range circuit and a next context rLPS circuit responsive to rLPS range, value and next context to obtain a next context rLPS value.

    摘要翻译： 一种用于执行h.264二进制解码符号指令的计算系统，包括具有范围归一化电路和rLPS更新电路的第一计算单元，并且响应于当前的rLPS，范围，值和当前上下文以第一模式操作以产生下一个 标准化范围和下一个rLPS为当前上下文; 第二计算单元，包括响应于当前rLPS，范围值和当前上下文的值更新电路，上下文更新电路和值归一化电路，以获得输出位，归一化值和更新的当前上下文; 以及第三计算单元或所述第一计算单元，其以第二模式操作，包括响应于rLPS范围，值和下一个上下文的范围电路和下一个上下文rLPS电路，以获得下一个上下文rLPS值。

    Programmable compute system for executing an H.264 binary decode symbol instruction
    8.
    发明申请
    Programmable compute system for executing an H.264 binary decode symbol instruction 有权
    用于执行H.264二进制解码符号指令的可编程计算系统

    公开(公告)号：US20080258947A1

    公开(公告)日：2008-10-23

    申请号：US11788094

    申请日：2007-04-19

    申请人： James Wilson ,  Joshua A. Kablotsky ,  Yosef Stein ,  Christopher M. Mayer

    发明人： James Wilson ,  Joshua A. Kablotsky ,  Yosef Stein ,  Christopher M. Mayer

    IPC分类号： H03M7/00

    CPC分类号： H03M7/4006

    摘要： A compute system for executing an h.264 binary decode symbol instruction including a first compute unit having a range normalization circuit and an rLPS update circuit, and operating in a first mode responsive to current rLPS, range, value and current context to generate the next normalized range and next rLPS for the current context; a second compute unit including a value update circuit, a context update circuit, and value normalization circuit responsive to current rLPS, range value and current context to obtain the output bit, normalized value and the updated current context; and a third compute unit or said first compute unit operating in a second mode including a range circuit and a next context rLPS circuit responsive to rLPS range, value and next context to obtain a next context rLPS value.

    摘要翻译： 一种用于执行h.264二进制解码符号指令的计算系统，包括具有范围归一化电路和rLPS更新电路的第一计算单元，并且响应于当前的rLPS，范围，值和当前上下文以第一模式操作以产生下一个 标准化范围和下一个rLPS为当前上下文; 第二计算单元，包括响应于当前rLPS，范围值和当前上下文的值更新电路，上下文更新电路和值归一化电路，以获得输出位，归一化值和更新的当前上下文; 以及第三计算单元或所述第一计算单元，其以第二模式操作，包括响应于rLPS范围，值和下一个上下文的范围电路和下一个上下文rLPS电路，以获得下一个上下文rLPS值。

    Iterative process with rotated architecture for reduced pipeline dependency
    9.
    发明申请
    Iterative process with rotated architecture for reduced pipeline dependency 审中-公开
    具有旋转架构的迭代过程，以减少管道依赖性

    公开(公告)号：US20080075376A1

    公开(公告)日：2008-03-27

    申请号：US11527001

    申请日：2006-09-26

    申请人： James Wilson ,  Joshua A. Kablotsky ,  Yosef Stein ,  Christopher M. Mayer

    发明人： James Wilson ,  Joshua A. Kablotsky ,  Yosef Stein ,  Christopher M. Mayer

    IPC分类号： G06K9/36 ,  G06K9/46

    CPC分类号： H04N19/436 ,  H04N19/13 ,  H04N19/61

    摘要： In a pipeline machine where, in an iterative process, one or more subsequent functions employ one or more parameters determined by one or more antecedent functions and the one or more subsequent functions generate one or more parameters for the one or more antecedent functions, pipeline dependency is reduced by advancing or rotating the iterative process by preliminarily providing to the subsequent function the next one or more parameters on which it is dependent and thereafter: generating by the subsequent function, in response to the one or more parameters on which is it dependent, the next one or more parameters required by the one or more antecedent functions and then, generating by the one or more antecedent functions, in response to the one or more parameters required by the one or more antecedent functions, the next one or more parameters for input to the subsequent function for the next iteration.

    摘要翻译： 在管线机器中，其中在迭代过程中，一个或多个后续功能采用由一个或多个先行函数确定的一个或多个参数，并且所述一个或多个后续函数为一个或多个先行函数生成一个或多个参数，流水线依赖 通过预先向随后的功能提供下一个或多个依赖于其的参数，然后：通过随后的功能生成响应于依赖于其的一个或多个参数，推进或旋转迭代过程， 所述一个或多个先行函数所需的下一个或多个参数，然后响应于所述一个或多个先行函数所需的一个或多个参数，由一个或多个先行函数生成下一个或多个参数，用于 输入下一次迭代的后续功能。

    METHODS AND APPARATUS FOR PERFORMING JUMP OPERATIONS IN A DIGITAL PROCESSOR
    10.
    发明申请
    METHODS AND APPARATUS FOR PERFORMING JUMP OPERATIONS IN A DIGITAL PROCESSOR 有权
    在数字处理器中执行跳闸操作的方法和装置

    公开(公告)号：US20100146248A1

    公开(公告)日：2010-06-10

    申请号：US12328484

    申请日：2008-12-04

    申请人： Christopher M. Mayer ,  Adil Bahadoor ,  Michael Long

    发明人： Christopher M. Mayer ,  Adil Bahadoor ,  Michael Long

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/3806 ,  G06F9/322 ,  G06F9/3844

    摘要： Methods and apparatus are provided for performing a jump operation in a pipelined digital processor. The method includes writing target addresses of jump instructions to be executed to a memory table, detecting a first jump instruction being executed by the processor, the first jump instruction referencing a pointer to a first target address in the memory table, the processor executing the first jump instruction by jumping to the first target address and modifying the pointer to point to a second target address in the memory table, the second target address corresponding to a second jump instruction. The execution of the first jump instruction may include prefetching at least one future target address from the memory table and writing the future target address in a local memory. The second target address may be accessed in the local memory in response to detection of the second jump instruction.

    摘要翻译： 提供了用于在流水线数字处理器中执行跳转操作的方法和装置。 该方法包括将要执行的跳转指令的目标地址写入存储表，检测由处理器执行的第一跳转指令，第一跳转指令引用指向存储表中第一目标地址的指针，处理器执行第一 通过跳转到第一目标地址并修改指针以指向存储表中的第二目标地址，跳转指令，第二目标地址对应于第二跳转指令。 第一跳转指令的执行可以包括从存储器表预取至少一个未来的目标地址，并将未来的目标地址写入本地存储器中。 响应于检测到第二跳转指令，可以在本地存储器中访问第二目标地址。