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公开(公告)号：US06441842B1
公开(公告)日：2002-08-27
申请号：US09098106
申请日：1998-06-16
IPC分类号： H04N714
摘要： According to one embodiment, a cost-effective videophone communicates over a POTS line, and generates video data in a format for a selected display type. The device includes a video source to capture images and to generate video data representing the images; a telephone line interface circuit, including a signal transmission circuit and a signal receiver circuit; to transmit and receive video data over the telephone line; a memory circuit for storing a main program including video data processing consistent with at least one video-coding recommendation and for processing pixels for a certain display type; a programmable processor circuit for executing the code for processing pixels for a certain display type and, in response, causing image data to be output for display. The programmable processor circuit has a DSP section for compressing and decompressing video, and a RISC-type processor section for general control.
摘要翻译： 根据一个实施例，经济有效的视频电话通过POTS线路进行通信，并以所选显示类型的格式生成视频数据。 该设备包括用于捕获图像并产生表示图像的视频数据的视频源; 电话线接口电路，包括信号传输电路和信号接收器电路; 通过电话线传输和接收视频数据; 存储电路，用于存储包括与至少一个视频编码推荐一致的视频数据处理并用于处理某种显示类型的像素的主程序; 可编程处理器电路，用于执行用于处理某种显示类型的像素的代码，并且作为响应，导致图像数据被输出以供显示。 可编程处理器电路具有用于压缩和解压缩视频的DSP部分和用于一般控制的RISC型处理器部分。
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公开(公告)号：US5790712A
公开(公告)日：1998-08-04
申请号：US908826
申请日：1997-08-08
摘要： A vision processor includes a control section, a motion estimation section, and a discrete cosine transform ("DCT") section. The motion estimation section includes two memories, an image memory with two read ports and a write port, and a search memory with two read ports and a write port. The DCT section includes a DCT memory configurable as a two read, two write port memory and as a four read, four write port memory. The ports of these memories are selectively applied to various elements in the motion estimation path and the DCT path. In motion vector searching, the ALU performs averaging and difference operations on pixels in the frame and search memories. Data from the search memory is shifted for certain operations, before arithmetic operations in the ALU are performed. In DCT operations, transposition is done on word data read from the DCT memory in a shifter/transposer, which is shared with the motion estimation section, and the results written back to the DCT memory through the ALU operating in pass through mode. Multiply-accumulate operations are done in a multiplier-accumulator, which reads and writes-back to the DCT memory. Data transfers from the frame and search memories to the DCT memory may be performed in parallel with multiply-accumulate operations.
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公开(公告)号：US07035890B2
公开(公告)日：2006-04-25
申请号：US10470571
申请日：2001-03-01
IPC分类号： G06F3/38
摘要： An apparatus for multiplying and accumulating numeric quantities, including a multiplier for receiving the numeric quantities, with the multiplier having a sum output and a carry output. A first shift register has an input coupled to the sum output of the multiplier, and a second shift register has an input coupled to the carry output of the multiplier. An adder and third shift register are used to complete processing of the apparatus' arithmetic operations.
摘要翻译： 一种用于乘数和累积数字量的装置，包括用于接收数字量的乘法器，乘法器具有和输出和进位输出。 第一移位寄存器具有耦合到乘法器的和输出的输入，并且第二移位寄存器具有耦合到乘法器的进位输出的输入。 使用加法器和第三移位寄存器来完成装置的算术运算的处理。
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公开(公告)号：US06965644B2
公开(公告)日：2005-11-15
申请号：US09797035
申请日：2001-03-01
摘要： A programmable motion estimator includes one dual ported memory for storing an image block, the prediction error, and a temporary block used in interpolation, and a pixel-group random access dual ported memory for storing a search window. The two ports of the two memories are selectively applied to an arithmetic logic unit, or ALU, through a multiplexer. One output of the ALU provides an absolute difference, which is furnished to a tree adder. Another output of the ALU provides an average value or a difference value, as selected, which is routed to the inputs of the image memory and the search memory. In motion vector searching, the ALU performs pixel absolute difference arithmetic using the pixel groups from the image memory and from the search memory, and determines a sum of absolute differences in the tree adder. In half pixel interpolation, the ALU performs pixel averaging arithmetic using pixel groups from the search memory, and writes back to the search memory. In quarter pixel interpolation, the ACU performs pixel averaging arithmetic using pixel groups from the image and search memories, and writes back to the search memory. In some quarter pixel interpolations, temporary interpolated blocks from the image memory are used to interpolated quarter pixel blocks. These temporary blocks are obtained by pixel averaging in the ALU using pixel groups from the search memory. In error prediction determination, the ALU performs pixel subtraction using the pixel groups from the image memory and from the search memory, and writes back to the image memory.
摘要翻译： 可编程运动估计器包括用于存储图像块的一个双端口存储器，预测误差和在插值中使用的临时块，以及用于存储搜索窗口的像素组随机存取双端口存储器。 两个存储器的两个端口通过多路复用器选择性地应用于算术逻辑单元或ALU。 ALU的一个输出提供绝对差异，它被提供给树加法器。 ALU的另一输出提供被选择的平均值或差值，其被路由到图像存储器和搜索存储器的输入。 在运动矢量搜索中，ALU使用来自图像存储器和搜索存储器的像素组来执行像素绝对差分运算，并且确定树加法器中的绝对差的和。 在半像素内插中，ALU使用来自搜索存储器的像素组来执行像素平均运算，并将其写回到搜索存储器。 在四分之一像素插值中，ACU使用来自图像和搜索存储器的像素组执行像素平均算术，并且将其写回到搜索存储器。 在一些四分之一像素插值中，来自图像存储器的临时内插块被用于内插四分之一像素块。 这些临时块通过使用来自搜索存储器的像素组在ALU中的像素平均来获得。 在错误预测确定中，ALU使用来自图像存储器和搜索存储器的像素组来执行像素相减，并将其写回图像存储器。
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公开(公告)号：US5379351A
公开(公告)日：1995-01-03
申请号：US838382
申请日：1992-02-19
摘要： A vision processor includes a control section, a motion estimation section, and a discrete cosine transform ("DCT") section. The motion estimation section includes two memories, an image memory with two read ports and a write port, and a search memory with two read ports and a write port. The DCT section includes a DCT memory configurable as a two read, two write port memory and as a four read, four write port memory. The ports of these memories are selectively applied to various elements in the motion estimation path and the DCT path. In motion vector searching, the ALU performs averaging and difference operations on pixels in the frame and search memories. Data from the search memory is shifted for certain operations, before arithmetic operations in the ALU are performed. In DCT operations, transposition is done on word data read from the DCT memory in a shifter/transposer, which is shared with the motion estimation section, and the results written back to the DCT memory through the ALU operating in pass through mode. Multiply-accumulate operations are done in a multiplier-accumulator, which reads and writes-back to the DCT memory. Data transfers from the frame and search memories to the DCT memory may be performed in parallel with multiply-accumulate operations.
摘要翻译： 视觉处理器包括控制部分，运动估计部分和离散余弦变换（“DCT”）部分。 运动估计部包括两个存储器，具有两个读取端口的图像存储器和写入端口，以及具有两个读取端口和写入端口的搜索存储器。 DCT部分包括可配置为两个读取，两个写入端口存储器和四个读取四个写入端口存储器的DCT存储器。 这些存储器的端口选择性地应用于运动估计路径和DCT路径中的各种元件。 在运动矢量搜索中，ALU对帧和搜索存储器中的像素执行平均和差分运算。 在执行ALU中的算术运算之前，来自搜索存储器的数据被移位以进行某些操作。 在DCT操作中，在与运动估计部分共享的移位器/转置器中从DCT存储器读取的字数据进行转置，并且结果通过以通过模式操作的ALU写回到DCT存储器。 乘法累加操作在乘法器累加器中完成，乘法器累加器读取和写回到DCT存储器。 从帧和搜索存储器到DCT存储器的数据传输可以与乘法累加操作并行执行。
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公开(公告)号：US5594813A
公开(公告)日：1997-01-14
申请号：US838380
申请日：1992-02-19
CPC分类号： G06T7/202 , H04N19/43 , H04N19/433 , H04N19/51 , H04N19/523 , H04N5/145 , G06T2207/10016
摘要： A programmable motion estimator includes one dual ported memory for storing an image block, the prediction error, and a temporary block used in interpolation, and a pixel-group random access dual ported memory for storing a search window. The two ports of the two memories are selectively applied to an arithmetic logic unit, or ALU, through a multiplexer. One output of the ALU provides an absolute difference, which is furnished to a tree adder. Another output of the ALU provides an average value or a difference value, as selected, which is routed to the inputs of the image memory and the search memory. In motion vector searching, the ALU performs pixel absolute difference arithmetic using the pixel groups from the image memory and from the search memory, and determines a sum of absolute differences in the tree adder. In half pixel interpolation, the ALU performs pixel averaging arithmetic using pixel groups from the search memory, and writes back to the search memory. In quarter pixel interpolation, the ACU performs pixel averaging arithmetic using pixel groups from the image and search memories, and writes back to the search memory. In some quarter pixel interpolations, temporary interpolated blocks from the image memory are used to interpolated quarter pixel blocks. These temporary blocks are obtained by pixel averaging in the ALU using pixel groups from the search memory. In error prediction determination, the ALU performs pixel subtraction using the pixel groups from the image memory and from the search memory, and writes back to the image memory.
摘要翻译： 可编程运动估计器包括用于存储图像块的一个双端口存储器，预测误差和在插值中使用的临时块，以及用于存储搜索窗口的像素组随机存取双端口存储器。 两个存储器的两个端口通过多路复用器选择性地应用于算术逻辑单元或ALU。 ALU的一个输出提供绝对差异，它被提供给树加法器。 ALU的另一输出提供被选择的平均值或差值，其被路由到图像存储器和搜索存储器的输入。 在运动矢量搜索中，ALU使用来自图像存储器和搜索存储器的像素组来执行像素绝对差分运算，并且确定树加法器中的绝对差的和。 在半像素内插中，ALU使用来自搜索存储器的像素组来执行像素平均运算，并将其写回到搜索存储器。 在四分之一像素插值中，ACU使用来自图像和搜索存储器的像素组执行像素平均算术，并且将其写回到搜索存储器。 在一些四分之一像素插值中，来自图像存储器的临时内插块被用于内插四分之一像素块。 这些临时块通过使用来自搜索存储器的像素组在ALU中的像素平均来获得。 在错误预测确定中，ALU使用来自图像存储器和搜索存储器的像素组来执行像素相减，并将其写回图像存储器。
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公开(公告)号：US5901248A
公开(公告)日：1999-05-04
申请号：US692993
申请日：1996-08-06
CPC分类号： G06T7/202 , H04N19/43 , H04N19/433 , H04N19/51 , H04N19/523 , H04N5/145 , G06T2207/10016
摘要： A programmable motion estimator includes one dual ported memory for storing an image block, the prediction error, and a temporary block used in interpolation, and a pixel-group random access dual ported memory for storing a search window. The two ports of the two memories are selectively applied to an arithmetic logic unit, or ALU, through a multiplexer. One output of the ALU provides an absolute difference, which is furnished to a tree adder. Another output of the ALU provides an average value or a difference value, as selected, which is routed to the inputs of the image memory and the search memory. Among other tasks, the programmable motion estimator performs motion vector searching, half pixel interpolation, quarter pixel interpolation and error prediction determination.
摘要翻译： 可编程运动估计器包括用于存储图像块的一个双端口存储器，预测误差和在插值中使用的临时块，以及用于存储搜索窗口的像素组随机存取双端口存储器。 两个存储器的两个端口通过多路复用器选择性地应用于算术逻辑单元或ALU。 ALU的一个输出提供绝对差异，它被提供给树加法器。 ALU的另一输出提供被选择的平均值或差值，其被路由到图像存储器和搜索存储器的输入。 在其他任务中，可编程运动估计器执行运动矢量搜索，半像素插值，四分之一像素插值和误差预测确定。
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公开(公告)号：US20050238098A1
公开(公告)日：2005-10-27
申请号：US11172633
申请日：2005-07-01
申请人： Jan Fandrianto , Chi Wang , Sehat Sutardja , Hedley Rainnie , Bryan Martin
发明人： Jan Fandrianto , Chi Wang , Sehat Sutardja , Hedley Rainnie , Bryan Martin
摘要： Consistent with one aspect, a circuit arrangement performs a variety of operations for tasks relating to motion estimation and includes memories having addressable locations (e.g., N pixels in width) and having various write and read ports, and various ALU components such as multiplexers and adders.
摘要翻译： 与一个方面一致，电路装置对与运动估计相关的任务执行各种操作，并且包括具有可寻址位置（例如，宽度为N个像素）并且具有各种写入和读取端口的存储器以及各种ALU组件，例如多路复用器和加法器 。
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公开(公告)号：US20060013316A1
公开(公告)日：2006-01-19
申请号：US11192823
申请日：2005-07-29
申请人： Jan Fandrianto , Chi Wang , Sehat Sutardja , Hedley Rainnie , Bryan Martin
发明人： Jan Fandrianto , Chi Wang , Sehat Sutardja , Hedley Rainnie , Bryan Martin
IPC分类号： H04N11/04
摘要： Consistent with one aspect, a circuit arrangement performs a variety of operations for tasks relating to motion and includes one or more ALU components. One such circuit arrangement is adapted to provide a picture phone that includes: a telephone transceiver; a camera; a display; a digital signal processor (DSP), including a multiplier unit, adapted to perform image data (de)compression; and a reduced instruction set computing (RISC) processor for routing data among the camera, the display, the DSP, and the telephone transceiver. Further, a memory is used to store (de)compression algorithm code executed by the DSP and data routing control code executed by the RISC processor
摘要翻译： 根据一个方面，电路装置对与运动相关的任务执行各种操作并且包括一个或多个ALU组件。 一种这样的电路装置适于提供一种图像电话，其包括：电话收发机; 相机; 一个显示器 数字信号处理器（DSP），包括适于执行图像数据（de）压缩的乘法器单元; 以及用于在相机，显示器，DSP和电话收发器之间路由数据的精简指令集计算（RISC）处理器。 此外，存储器用于存储由DSP执行的压缩算法代码和由RISC处理器执行的数据路由控制代码
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公开(公告)号：US20240356499A1
公开(公告)日：2024-10-24
申请号：US18622565
申请日：2024-03-29
申请人： Sehat Sutardja
发明人： Sehat Sutardja
CPC分类号： H03F1/565 , H03F3/245 , H03F2200/222 , H03F2200/387 , H03F2200/451
摘要： An amplifier system comprising an input matching network configured to receive an input signal from a signal source. The input matching network is configured to impedance match between the amplifier system and the signal source. An input transformer is configured to receive the impedance matched input signal and perform voltage step down and current step up. An amplifier is configured to receive and amplify an output signal from the input transformer to generate an amplified signal. A low winding ratio output transformer provides isolation between an antenna and amplifier. An output matching network is configured to impedance match to an antenna and provide voltage step up. The input transformer may have a ratio of 2N:N, such as 2:1 ratio. At least one center tap of the input transformer may connect to a bias voltage. The amplifier system may be configured for operation in the radio frequency band.
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