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公开(公告)号：US4507726A
公开(公告)日：1985-03-26
申请号：US342630
申请日：1982-01-26
CPC分类号： G06F15/8023
摘要： The Array Processor of the present invention is comprised of a plurality of modular Elemental Processors, the modules being of a number of different functional types. These modules are associated so that the Elemental Processors are architecturally parallel to one another. The principal flow of data within the Array Processor, based on the simultaneous transfer of data words within the Elemental Processors, is thereby correspondingly parallel. The modules are also architecturally associated as functional planes that lie transverse to the Elemental Processors. Each functional plane is thereby comprised of an array of modules that are each otherwise associated with a separate Elemental Processor. Further, the modules of a given functional plane are of a single functional type. This allows the data of a two-dimensionally structured data set, present within the Array Processor, to be processed identically and in parallel by a common logical operation as provided and performed by a functional plane.The Array Processor is operatively connected to a Control Processor by an Array/Control Processor Interface. This interface allows the Control Processor to direct the operation of, and exchange data with, the Array Processor.
摘要翻译： 本发明的阵列处理器由多个模块化元件处理器组成，该模块具有许多不同的功能类型。 这些模块相关联，使得元素处理器在架构上彼此平行。 因此，基于元素处理器内的数据字的同时传送，阵列处理器内的主要数据流相应地并行。 模块也在架构上与作为横向于元素处理器的功能平面相关联。 因此，每个功能平面由各自以独立元件处理器相关联的模块阵列组成。 此外，给定功能平面的模块是单一功能类型。 这允许存在于阵列处理器内的二维结构化数据集的数据通过由功能平面提供和执行的公共逻辑操作相同地并行地进行处理。 阵列处理器通过阵列/控制处理器接口可操作地连接到控制处理器。 该接口允许控制处理器指导数组处理器的操作和与数据处理器交换数据。
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公开(公告)号：US4498134A
公开(公告)日：1985-02-05
申请号：US342671
申请日：1982-01-26
CPC分类号： G06F15/8023
摘要： A Segregator Functional Plane capable of dynamically segregating any number, or subset, of a Modular Array Processor's functional planes, either in terms of control or data exchange, or both, from the remainder. This is provided by interspersing a number of Segregator Functional Planes throughout the Array Processor so that a Segregator Functional Plane is architecturally located between each of the adjacent subsets of the Array Processor's functional planes. The Segregator Functional Plane nominally includes an array of pseudomodules that corresponds to the module arrays of the other functional planes of the Array Processor so that a pseudo-module is architecturally present between correspondingly adjacent modules of each Elemental Processor. These pseudo-modules are comprised of switches that may be commonly activated to functionally sever their respective Elemental Processor data bus lines. The Segregator Functional Plane also includes a second set of commonly activatable switches for functionally severing each of the Address Bus, Control Bus, Clock, Address Valid, and Configuration Latch Reset lines. Further, a third set of commonly activatable switches are included within the Segregator Functional Plane for functionally severing the input and output data lines that interconnect the Control and Array Processors.
摘要翻译： 分离器功能平面，能够从其余部分动态地分离模块化阵列处理器的功能平面的任何数量或子集，无论是在控制或数据交换方面，还是两者。 这是通过在整个阵列处理器中散布多个隔离器功能平面来提供的，以便分离器功能平面在架构上位于阵列处理器功能平面的每个相邻子集之间。 分隔符功能平面名义上包括对应于阵列处理器的其他功能平面的模块阵列的伪模块阵列，使得伪模块在架构上存在于每个元件处理器的相应的相邻模块之间。 这些伪模块由可以通常被激活以切换其各自的元素处理器数据总线的开关组成。 分离器功能平面还包括第二组常用的可激活开关，用于功能性地切断每个地址总线，控制总线，时钟，地址有效和配置锁存复位线。 此外，分离器功能平面中还包括第三组常用的可激活开关，用于功能性地切断连接控制和阵列处理器的输入和输出数据线。
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3.发明授权Column shorted and full array shorted functional plane for use in a modular array processor and method for using same 失效用于模块化阵列处理器的列短路和全阵列短路功能平面及其使用方法
公开(公告)号：US4745546A
公开(公告)日：1988-05-17
申请号：US392207
申请日：1982-06-25
CPC分类号： G06F15/8023
摘要： A column shorted and full array shorted functional plane for simultaneously transferring, or shorting, data to and from the data exchange subsystems of the array processor. This functional plane nominally includes an array of pseudo-modules that architecturally corresponds to the module arrays of the other functional planes of the array processor. Thus, a pseudo-module is present in each of the elemental processors. These pseudo-modules are associated as columns that are each interconnected by a shorted plane column data exchange subsystem. These columns are, in turn, associated with column control logic circuits that each include a column memory register. A mode decode logic circuit establishes the operating configuration of the column control logic circuits.
摘要翻译： 列阵短路和全阵列短路功能平面，用于同时向数组处理器的数据交换子系统传输或缩短数据。 该功能平面名义上包括在阵列处理器的其他功能平面的架构上对应的伪模块阵列。 因此，每个元素处理器中都存在伪模块。 这些伪模块作为列互连，每个列通过短路平面列数据交换子系统互连。 这些列又与列控制逻辑电路相关联，每个列控制逻辑电路都包括列存储器寄存器。 模式解码逻辑电路建立列控制逻辑电路的操作配置。
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