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公开(公告)号：US4507726A
公开(公告)日：1985-03-26
申请号：US342630
申请日：1982-01-26
CPC分类号： G06F15/8023
摘要： The Array Processor of the present invention is comprised of a plurality of modular Elemental Processors, the modules being of a number of different functional types. These modules are associated so that the Elemental Processors are architecturally parallel to one another. The principal flow of data within the Array Processor, based on the simultaneous transfer of data words within the Elemental Processors, is thereby correspondingly parallel. The modules are also architecturally associated as functional planes that lie transverse to the Elemental Processors. Each functional plane is thereby comprised of an array of modules that are each otherwise associated with a separate Elemental Processor. Further, the modules of a given functional plane are of a single functional type. This allows the data of a two-dimensionally structured data set, present within the Array Processor, to be processed identically and in parallel by a common logical operation as provided and performed by a functional plane.The Array Processor is operatively connected to a Control Processor by an Array/Control Processor Interface. This interface allows the Control Processor to direct the operation of, and exchange data with, the Array Processor.
摘要翻译： 本发明的阵列处理器由多个模块化元件处理器组成，该模块具有许多不同的功能类型。 这些模块相关联，使得元素处理器在架构上彼此平行。 因此，基于元素处理器内的数据字的同时传送，阵列处理器内的主要数据流相应地并行。 模块也在架构上与作为横向于元素处理器的功能平面相关联。 因此，每个功能平面由各自以独立元件处理器相关联的模块阵列组成。 此外，给定功能平面的模块是单一功能类型。 这允许存在于阵列处理器内的二维结构化数据集的数据通过由功能平面提供和执行的公共逻辑操作相同地并行地进行处理。 阵列处理器通过阵列/控制处理器接口可操作地连接到控制处理器。 该接口允许控制处理器指导数组处理器的操作和与数据处理器交换数据。
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公开(公告)号：US4498134A
公开(公告)日：1985-02-05
申请号：US342671
申请日：1982-01-26
CPC分类号： G06F15/8023
摘要： A Segregator Functional Plane capable of dynamically segregating any number, or subset, of a Modular Array Processor's functional planes, either in terms of control or data exchange, or both, from the remainder. This is provided by interspersing a number of Segregator Functional Planes throughout the Array Processor so that a Segregator Functional Plane is architecturally located between each of the adjacent subsets of the Array Processor's functional planes. The Segregator Functional Plane nominally includes an array of pseudomodules that corresponds to the module arrays of the other functional planes of the Array Processor so that a pseudo-module is architecturally present between correspondingly adjacent modules of each Elemental Processor. These pseudo-modules are comprised of switches that may be commonly activated to functionally sever their respective Elemental Processor data bus lines. The Segregator Functional Plane also includes a second set of commonly activatable switches for functionally severing each of the Address Bus, Control Bus, Clock, Address Valid, and Configuration Latch Reset lines. Further, a third set of commonly activatable switches are included within the Segregator Functional Plane for functionally severing the input and output data lines that interconnect the Control and Array Processors.
摘要翻译： 分离器功能平面，能够从其余部分动态地分离模块化阵列处理器的功能平面的任何数量或子集，无论是在控制或数据交换方面，还是两者。 这是通过在整个阵列处理器中散布多个隔离器功能平面来提供的，以便分离器功能平面在架构上位于阵列处理器功能平面的每个相邻子集之间。 分隔符功能平面名义上包括对应于阵列处理器的其他功能平面的模块阵列的伪模块阵列，使得伪模块在架构上存在于每个元件处理器的相应的相邻模块之间。 这些伪模块由可以通常被激活以切换其各自的元素处理器数据总线的开关组成。 分离器功能平面还包括第二组常用的可激活开关，用于功能性地切断每个地址总线，控制总线，时钟，地址有效和配置锁存复位线。 此外，分离器功能平面中还包括第三组常用的可激活开关，用于功能性地切断连接控制和阵列处理器的输入和输出数据线。
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3.发明授权Modular input-programmable logic circuits for use in a modular array processor 失效用于模块化阵列处理器的模块化输入可编程逻辑电路
公开(公告)号：US4524428A
公开(公告)日：1985-06-18
申请号：US342639
申请日：1982-01-26
申请人： Jan Grinberg , Siegfried Hansen
发明人： Jan Grinberg , Siegfried Hansen
CPC分类号： G06F7/575 , G06F15/8023
摘要： A general circuit design for the various functional types of modules used in the Elemental Processors of a Modular Array Processor. These modules nominally include an input-programmable logic circuit and closely associated memory register. They also include a common means of transferring data to and from a data bus for communicating data to the other modules present within their respective Elemental Processors. The various functional types of modules are realized through the use of logic circuits of different specific designs. Each particular type of logic circuit is designed to implement all of the related logical and data manipulative operations necessary to provide a general data processing function, such as those of accumulator, memory, counter, and comparator. This allows the logic circuit to receive data from the data bus, perform a selected data manipulation operation consistent with the module's functional type on the data received in combination with data stored in the memory register and to store the resultant data in the memory register, and to transmit the stored resultant data back to the data bus.
摘要翻译： 用于模块化阵列处理器的元件处理器中使用的各种功能类型的模块的通用电路设计。 这些模块名义上包括输入可编程逻辑电路和密切相关的存储器寄存器。 它们还包括将数据传输到数据总线和从数据总线传送数据到其各自元件处理器中存在的其他模块的常用方法。 模块的各种功能类型通过使用不同特定设计的逻辑电路来实现。 每个特定类型的逻辑电路被设计成实现提供诸如累加器，存储器，计数器和比较器的一般数据处理功能所必需的所有相关逻辑和数据操作操作。 这允许逻辑电路从数据总线接收数据，对存储在存储器寄存器中的数据结合数据接收的数据执行与模块的功能类型一致的选择的数据操作操作，并将结果数据存储在存储器寄存器中，以及 将所存储的结果数据发送回数据总线。
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公开(公告)号：US4003640A
公开(公告)日：1977-01-18
申请号：US589510
申请日：1975-06-23
申请人： Siegfried Hansen
发明人： Siegfried Hansen
CPC分类号： G02B26/06
摘要： Electro-hydraulic driver has an electro-mechanical actuator which controls the hydraulic fluid flow control orifice. The hydraulic fluid orifice is an annulus which is connected to a cylinder having minimum volume which is supplied from a hydraulic source through a flow restriction. The piston acts against a spring so that with electrical actuation, piston motion is controlled.
摘要翻译： 电动液压驱动器具有控制液压流体流量控制孔的机电致动器。 液压流体孔口是连接到具有最小体积的气缸的环形空间，其通过流动限制从液压源供应。 活塞作用在弹簧上，因此通过电动执行，活塞运动受到控制。
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公开(公告)号：US4543642A
公开(公告)日：1985-09-24
申请号：US342640
申请日：1982-01-26
申请人： Siegfried Hansen
发明人： Siegfried Hansen
CPC分类号： G06F15/8023
摘要： A Data Exchange Subsystem comprising a data bus for transferring data signals, a load for normally maintaining a logical one signal on the data bus, a number of data receivers operatively connected to the data bus for sensing the logic state of the data signal, and a number of data transmitters operatively connected to the data bus for driving their respective data onto the bus. The data transmitter utilize open collector output buffers to force the data signal to a logical zero in response to corresponding data provided to the respective data transmitters, thereby collectively forming a "wired-and" structure, providing the Data Exchange Subsystem with an inherent data conflict resolving capability that may be utilized in data-dependent operations such as data masking.
摘要翻译： 一种数据交换子系统，包括用于传送数据信号的数据总线，用于在数据总线上正常保持逻辑1信号的负载，可操作地连接到数据总线的多个数据接收器，用于感测数据信号的逻辑状态，以及 数据发射器的数量可操作地连接到数据总线，用于将它们各自的数据驱动到总线上。 数据发射机利用集电极开路输出缓冲器来响应于提供给各个数据发射机的相应数据而将数据信号强制为逻辑零，从而共同形成“有线和”结构，为数据交换子系统提供固有的数据冲突 可用于数据相关操作（如数据屏蔽）中的解析能力。
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公开(公告)号：US4528490A
公开(公告)日：1985-07-09
申请号：US407024
申请日：1982-08-11
申请人： Siegfried Hansen
发明人： Siegfried Hansen
CPC分类号： H01L21/68
摘要： Stage 12 is moved into position by traction of capstan 38 on bar 42 which is pivoted under intermediate plate 20, and by traction on bar 66 which is pivoted under stage plate 12. Bar 42 is pressed against motor driven capstan 38 by pressure rollers 44 and 46. The pressure rollers are mounted on a rotatable yoke 50 so that the bar can freely swing and only applies longitudinal forces to the plate. This same structure is provided for drive bar 66.
摘要翻译： 阶段12通过在杆42上牵引的杆36移动到位，该杆42在中间板20下枢转，并且通过牵引力在杆板66上枢转的杆66上。杆42通过压力辊44和 压力辊安装在可旋转的轭50上，使得杆可以自由摆动并且仅对板施加纵向力。 为驱动杆66提供相同的结构。
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公开(公告)号：US3952979A
公开(公告)日：1976-04-27
申请号：US551210
申请日：1975-02-19
申请人： Siegfried Hansen
发明人： Siegfried Hansen
摘要： Isolation of a platform from a base is achieved by employing six supports therebetween which preferably comprise two sets of three mutually perpendicular supports. The supports can be varied in length by a motor to control the platform in all six degrees of freedom (three translational and three rotational) with respect to the base.
摘要翻译： 通过在其间采用六个支撑件来实现平台从基座的隔离，其优选地包括两组三个相互垂直的支撑件。 支撑件可以通过马达在长度上变化，以相对于基座的所有六个自由度（三个平移和三个旋转）来控制平台。
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