摘要:
A Data Exchange Subsystem comprising a data bus for transferring data signals, a load for normally maintaining a logical one signal on the data bus, a number of data receivers operatively connected to the data bus for sensing the logic state of the data signal, and a number of data transmitters operatively connected to the data bus for driving their respective data onto the bus. The data transmitter utilize open collector output buffers to force the data signal to a logical zero in response to corresponding data provided to the respective data transmitters, thereby collectively forming a "wired-and" structure, providing the Data Exchange Subsystem with an inherent data conflict resolving capability that may be utilized in data-dependent operations such as data masking.
摘要:
Stage 12 is moved into position by traction of capstan 38 on bar 42 which is pivoted under intermediate plate 20, and by traction on bar 66 which is pivoted under stage plate 12. Bar 42 is pressed against motor driven capstan 38 by pressure rollers 44 and 46. The pressure rollers are mounted on a rotatable yoke 50 so that the bar can freely swing and only applies longitudinal forces to the plate. This same structure is provided for drive bar 66.
摘要:
The Array Processor of the present invention is comprised of a plurality of modular Elemental Processors, the modules being of a number of different functional types. These modules are associated so that the Elemental Processors are architecturally parallel to one another. The principal flow of data within the Array Processor, based on the simultaneous transfer of data words within the Elemental Processors, is thereby correspondingly parallel. The modules are also architecturally associated as functional planes that lie transverse to the Elemental Processors. Each functional plane is thereby comprised of an array of modules that are each otherwise associated with a separate Elemental Processor. Further, the modules of a given functional plane are of a single functional type. This allows the data of a two-dimensionally structured data set, present within the Array Processor, to be processed identically and in parallel by a common logical operation as provided and performed by a functional plane.The Array Processor is operatively connected to a Control Processor by an Array/Control Processor Interface. This interface allows the Control Processor to direct the operation of, and exchange data with, the Array Processor.
摘要:
A Segregator Functional Plane capable of dynamically segregating any number, or subset, of a Modular Array Processor's functional planes, either in terms of control or data exchange, or both, from the remainder. This is provided by interspersing a number of Segregator Functional Planes throughout the Array Processor so that a Segregator Functional Plane is architecturally located between each of the adjacent subsets of the Array Processor's functional planes. The Segregator Functional Plane nominally includes an array of pseudomodules that corresponds to the module arrays of the other functional planes of the Array Processor so that a pseudo-module is architecturally present between correspondingly adjacent modules of each Elemental Processor. These pseudo-modules are comprised of switches that may be commonly activated to functionally sever their respective Elemental Processor data bus lines. The Segregator Functional Plane also includes a second set of commonly activatable switches for functionally severing each of the Address Bus, Control Bus, Clock, Address Valid, and Configuration Latch Reset lines. Further, a third set of commonly activatable switches are included within the Segregator Functional Plane for functionally severing the input and output data lines that interconnect the Control and Array Processors.
摘要:
Isolation of a platform from a base is achieved by employing six supports therebetween which preferably comprise two sets of three mutually perpendicular supports. The supports can be varied in length by a motor to control the platform in all six degrees of freedom (three translational and three rotational) with respect to the base.
摘要:
A general circuit design for the various functional types of modules used in the Elemental Processors of a Modular Array Processor. These modules nominally include an input-programmable logic circuit and closely associated memory register. They also include a common means of transferring data to and from a data bus for communicating data to the other modules present within their respective Elemental Processors. The various functional types of modules are realized through the use of logic circuits of different specific designs. Each particular type of logic circuit is designed to implement all of the related logical and data manipulative operations necessary to provide a general data processing function, such as those of accumulator, memory, counter, and comparator. This allows the logic circuit to receive data from the data bus, perform a selected data manipulation operation consistent with the module's functional type on the data received in combination with data stored in the memory register and to store the resultant data in the memory register, and to transmit the stored resultant data back to the data bus.
摘要:
Electro-hydraulic driver has an electro-mechanical actuator which controls the hydraulic fluid flow control orifice. The hydraulic fluid orifice is an annulus which is connected to a cylinder having minimum volume which is supplied from a hydraulic source through a flow restriction. The piston acts against a spring so that with electrical actuation, piston motion is controlled.