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公开(公告)号：US09406399B2
公开(公告)日：2016-08-02
申请号：US14729238
申请日：2015-06-03
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
CPC classification number: G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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公开(公告)号：US11114177B2
公开(公告)日：2021-09-07
申请号：US16906286
申请日：2020-06-19
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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公开(公告)号：US09793007B2
公开(公告)日：2017-10-17
申请号：US15090664
申请日：2016-04-05
Applicant: Japan Display Inc.
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroyuki Higashijima , Yoshihiro Kotani , Shuuichirou Matsumoto
CPC classification number: G11C19/287 , G09G3/3677 , G09G5/003 , G09G2310/0286 , G09G2310/08 , G09G2330/021
Abstract: A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V(n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.
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公开(公告)号：US20160307642A1
公开(公告)日：2016-10-20
申请号：US15195000
申请日：2016-06-28
Inventor： Takahiro OCHIAI , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
CPC classification number: G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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公开(公告)号：US09881691B2
公开(公告)日：2018-01-30
申请号：US15195000
申请日：2016-06-28
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
CPC classification number: G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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Patent Agency Ranking
公开(公告)号：US11532371B2
公开(公告)日：2022-12-20
申请号：US17394475
申请日：2021-08-05
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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公开(公告)号：US10726933B2
公开(公告)日：2020-07-28
申请号：US16238771
申请日：2019-01-03
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
Abstract: A plurality of cascade-connected register circuits which comprises a bidirectional shift register include a top register circuit, a bottom register circuit, and main register circuits. The register circuit has an output circuit which outputs one of four-phase clock pulses when a voltage of a first node is an active level; a second output circuit which outputs a non-active level when a voltage of a second node is the active level; a second node reset circuit which sets the second node to the non-active level when a voltage of a second node reset terminal is the active level. The forward scan signal sets the voltage of the first node of the top register circuit to the active level, and the forward scan signal sets the voltage of the second node reset terminal of the bottom register circuit to the active level.
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公开(公告)号：US08982033B2
公开(公告)日：2015-03-17
申请号：US14449348
申请日：2014-08-01
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
CPC classification number: G09G3/3648 , G09G3/3674 , G09G2310/0286 , G09G2310/066 , G09G2330/025 , G11C19/184 , G11C19/28
Abstract: A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.
Abstract translation: 一种显示装置，包括用于输出各种脉冲和触发的各种部分，电路和其它装置，用于控制前向移位和向后移位操作。
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公开(公告)号：US12057181B2
公开(公告)日：2024-08-06
申请号：US18074556
申请日：2022-12-05
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
CPC classification number: G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A shift register circuit, including: a plurality of clock signal lines each supplying a clock pulse respectively; a plurality of cascade-connected register circuits including a top register circuit, and main register circuits providing between the top register circuit and the bottom register circuit; and a forward scan signal line supplying a forward scan signal to the plurality of cascade-connected register circuits.
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公开(公告)号：US10210945B2
公开(公告)日：2019-02-19
申请号：US15848052
申请日：2017-12-20
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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