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公开(公告)号：US11532371B2
公开(公告)日：2022-12-20
申请号：US17394475
申请日：2021-08-05
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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公开(公告)号：US10726933B2
公开(公告)日：2020-07-28
申请号：US16238771
申请日：2019-01-03
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
Abstract: A plurality of cascade-connected register circuits which comprises a bidirectional shift register include a top register circuit, a bottom register circuit, and main register circuits. The register circuit has an output circuit which outputs one of four-phase clock pulses when a voltage of a first node is an active level; a second output circuit which outputs a non-active level when a voltage of a second node is the active level; a second node reset circuit which sets the second node to the non-active level when a voltage of a second node reset terminal is the active level. The forward scan signal sets the voltage of the first node of the top register circuit to the active level, and the forward scan signal sets the voltage of the second node reset terminal of the bottom register circuit to the active level.
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公开(公告)号：US09928792B2
公开(公告)日：2018-03-27
申请号：US15497286
申请日：2017-04-26
Applicant: Japan Display Inc.
Inventor： Takayuki Suzuki , Hiroyuki Abe , Masahiro Maki , Mitsuru Goto
IPC: G06F3/044 , G09G3/36 , G06F3/041 , G02F1/1362 , G02F1/1333 , G02F1/1335 , G02F1/133
CPC classification number: G09G3/3655 , G02F1/13306 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133528 , G02F1/136286 , G02F2001/133302 , G02F2201/121 , G02F2201/123 , G02F2202/104 , G06F3/0412 , G06F3/0418 , G06F3/044 , G06F2203/04103 , G09G3/36 , G09G2300/0426 , G09G2320/0219 , G09G2320/0626
Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.
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公开(公告)号：US09715153B2
公开(公告)日：2017-07-25
申请号：US15176754
申请日：2016-06-08
Applicant: Japan Display Inc.
Inventor： Takahiro Ochiai , Mitsuru Goto
IPC: G02F1/1345 , G02F1/1333 , G02F1/13 , H01L23/00 , G02F1/1368 , G02F1/1343 , H01L27/12 , G02F1/1362
CPC classification number: G02F1/13452 , G02F1/133345 , G02F1/13439 , G02F1/13458 , G02F1/1368 , G02F2001/136254 , H01L24/05 , H01L24/06 , H01L27/124
Abstract: A display device includes a transparent substrate having a display region with a plurality of scanning signal lines and video signal lines intersecting thereon, a first terminal formed outside the display region connecting to a first terminal wiring and a second terminal wiring connected to a semiconductor chip, and an inverted staggered thin film transistor. The first terminal includes a first portion, a second portion on the first portion, a third portion having an exposed planar terminal plate on the second portion, a plurality of first vias between the first portion and the second portion, and a plurality of second vias between the second portion and the third portion. The first portion is connected to the first and second terminal wirings, and each of the plurality of first vias is not overlapped with each of the plurality of second vias in plan view.
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公开(公告)号：US09372375B2
公开(公告)日：2016-06-21
申请号：US14050562
申请日：2013-10-10
Inventor： Mitsuru Goto , Hiroko Hayata
IPC: G02F1/1345 , G02F1/1362 , G02F1/1335 , G09G3/36
CPC classification number: G02F1/13454 , G02F1/133617 , G02F1/13452 , G02F1/1362 , G09G3/3611 , G09G3/3614 , G09G3/3648 , G09G3/3688 , G09G2310/027 , G09G2310/0289 , G09G2310/0297
Abstract: A display device includes a TFT substrate with gate signal lines, drain signal lines, thin-film transistors connected thereto, a gate driver connected to the gate signal lines, a drain driver having output terminals connected to drain signal lines, and a film substrate having first wirings. The first wirings are disposed between the drain driver and the film substrate. The drain driver is mounted on the film substrate, and the output terminals are connected to the first wirings between the film substrate and the drain driver. The output terminal includes first group terminals formed in parallel with a longer edge of the drain driver, and second group terminals formed in parallel with the longer edge and disposed between the loner edge and the first group terminals.
Abstract translation: 显示装置包括具有栅极信号线的TFT基板，漏极信号线，与其连接的薄膜晶体管，连接到栅极信号线的栅极驱动器，具有连接到漏极信号线的输出端子的漏极驱动器，以及具有 第一条布线 第一配线设置在漏极驱动器和薄膜基板之间。 漏极驱动器安装在薄膜基板上，并且输出端子连接到薄膜基板和漏极驱动器之间的第一布线。 输出端子包括与漏极驱动器的较长边缘平行地形成的第一组端子，以及与较长边缘平行地形成并且设置在孤立边缘和第一组端子之间的第二组端子。
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Patent Agency Ranking
公开(公告)号：US08982033B2
公开(公告)日：2015-03-17
申请号：US14449348
申请日：2014-08-01
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
CPC classification number: G09G3/3648 , G09G3/3674 , G09G2310/0286 , G09G2310/066 , G09G2330/025 , G11C19/184 , G11C19/28
Abstract: A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.
Abstract translation: 一种显示装置，包括用于输出各种脉冲和触发的各种部分，电路和其它装置，用于控制前向移位和向后移位操作。
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公开(公告)号：US08922468B2
公开(公告)日：2014-12-30
申请号：US14159472
申请日：2014-01-21
Inventor： Mitsuru Goto , Hiroshi Katayanagi , Yukihide Ode , Yoshiyuki Saitou , Koichi Kotera
IPC: G09G3/36
CPC classification number: G09G3/3696 , G09G3/3614 , G09G3/3688 , G09G2310/027 , G09G2310/0289
Abstract: A semiconductor integrated circuit including a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two horizontal scanning lines.
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公开(公告)号：US10593276B2
公开(公告)日：2020-03-17
申请号：US16161909
申请日：2018-10-16
Applicant: Japan Display Inc.
Inventor： Takayuki Suzuki , Hiroyuki Abe , Masahiro Maki , Mitsuru Goto
IPC: G06F3/044 , G09G3/36 , G06F3/041 , G02F1/133 , G02F1/1333 , G02F1/1335 , G02F1/1362
Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.
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公开(公告)号：US09881691B2
公开(公告)日：2018-01-30
申请号：US15195000
申请日：2016-06-28
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
CPC classification number: G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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公开(公告)号：US09214115B2
公开(公告)日：2015-12-15
申请号：US14526807
申请日：2014-10-29
Applicant: Japan Display Inc.
Inventor： Takayuki Suzuki , Hiroyuki Abe , Masahiro Maki , Mitsuru Goto
CPC classification number: G09G3/3655 , G02F1/13306 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133528 , G02F1/136286 , G02F2001/133302 , G02F2201/121 , G02F2201/123 , G02F2202/104 , G06F3/0412 , G06F3/0418 , G06F3/044 , G06F2203/04103 , G09G3/36 , G09G2300/0426 , G09G2320/0219 , G09G2320/0626
Abstract: A display device includes a substrate having an image display area, pixel electrodes formed in the image display area of the substrate, a common electrode formed in the image display area of the substrate, inside signal lines formed inside the image display area of the substrate and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area of the substrate and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area of the substrate and electrically connected to the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines include a first portion, and a second portion that is higher in electric resistance than an electric resistance of the first portion, and the second portion has a bend.
Abstract translation: 显示装置包括具有图像显示区域的基板，形成在基板的图像显示区域中的像素电极，形成在基板的图像显示区域中的公共电极，形成在基板的图像显示区域内的信号线内部;以及 电连接到像素电极，形成在基板的图像显示区域外部并电连接到内部信号线的外部信号线，以及形成在基板的图像显示区域的内部和外部的公共线，并且电连接到公共电极 。 在内部信号线和公共电极之间形成耦合电容。 外部信号线包括第一部分和电阻高于第一部分的电阻的第二部分，并且第二部分具有弯曲部。
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