公开(公告)号：US12159575B2

公开(公告)日：2024-12-03

申请号：US18480528

申请日：2023-10-04

Applicant: Japan Display Inc.

Inventor： Kenji Harada ,  Tetsuo Morita

IPC: G09G3/3225

Abstract: According to one embodiment, a display device includes a pixel circuit provided in each of a plurality of pixels, a plurality of flip-flop circuits provided in a shift register and a reset element provided in each of the flip-flop circuits, and the reset element is an n-channel type transistor, the pixel circuit includes a light emitting element, a light emitting power supply and a switch element, and the light emitting element is disconnected from the light emitting power supply while the light emitting power supply is rising.

公开(公告)号：US11688337B2

公开(公告)日：2023-06-27

申请号：US17696941

申请日：2022-03-17

Applicant: Japan Display Inc.

Inventor： Kenji Harada ,  Tetsuo Morita

IPC: G09G3/3208

CPC classification number: G09G3/3208 ,  G09G2300/0452 ,  G09G2300/0842 ,  G09G2310/08

Abstract: A bootstrap circuit includes a first transistor including a gate electrode, a first and a second electrodes, a capacitor connected between the gate electrode and the second electrode, and a second transistor connected to the gate electrode. In a first period, the second transistor is turned on and the gate electrode is supplied with a first analog voltage, the first transistor is turned on, and the second electrode is supplied with a precharge voltage smaller than the first analog voltage from the first electrode. In a second period, the second transistor is turned off, the first electrode is supplied with a second analog voltage, the capacitor supplies a third analog voltage to the gate electrode in response to the first analog voltage and the second analog voltage, and the second electrode is supplied with the second analog voltage from the first electrode.

公开(公告)号：US20140225819A1

公开(公告)日：2014-08-14

申请号：US14171053

申请日：2014-02-03

Applicant: Japan Display Inc.

Inventor： Takahiro ONUMA ,  Kenji Harada ,  Satoshi Maruyama

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3648 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2310/0205 ,  G09G2310/0213 ,  G09G2310/0251

Abstract: Data lines are connected to pixels arranged on both sides of the data lines respectively, a cth gate line and a (c+1)th gate line are connected respectively to pixels arranged between the cth gate line and the (c+1)th gate line alternately, in the case of displaying an image at a Nth frame, the first gate line driver circuit and the second gate line driver circuit supply the gate signal to the cth gate line and the (c+1)th gate line in this order, and in the case of displaying an image at a (N+1)th frame, the first gate line driver circuit and the second gate line driver circuit supply the gate signal to the (c+1)th gate line and the cth gate line in this order.

Abstract translation: 数据线分别连接到排列在数据线两侧的像素，第c栅极线和第（c + 1）栅极线分别连接到布置在第c栅极线和第（c + 1）栅极之间的像素 在第N帧显示图像的情况下，第一栅极线驱动电路和第二栅极线驱动电路按照该顺序向第c栅极线和第（c + 1）栅极线提供栅极信号 并且在第（N + 1）帧显示图像的情况下，第一栅极线驱动电路和第二栅极线驱动电路向第（c + 1）栅极线和第C栅极提供栅极信号 按此顺序排列。

公开(公告)号：US09810933B2

公开(公告)日：2017-11-07

申请号：US14338064

申请日：2014-07-22

Applicant: JAPAN DISPLAY INC.

Inventor： Kenji Harada

IPC: G06F3/038 ,  G09G5/00 ,  G02F1/133 ,  G09G3/36

CPC classification number: G02F1/13306 ,  G09G3/3655 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0245 ,  G09G2310/0297

Abstract: A liquid crystal display device includes a plurality of common electrodes arranged so as to counter pixel electrodes extending in the row direction on a substrate. First and second voltage supply lines to supply first and second voltages to the common electrodes are connected with the common electrodes through a first switch circuit. A second switch circuit is arranged between the first voltage supply line and signal lines to switch a connection between the first voltage supply line and the signal lines. A gate open circuit is connected to scan lines to simultaneously supply a signal to switch on the pixel electrodes to all the scan lines. In case the power supply of the liquid crystal display device is turned off, a control circuit starts the power OFF driving operation to set the potential of the pixel electrode and the common electrode to substantially same by switching the first and second switch circuits.

公开(公告)号：US12035571B2

公开(公告)日：2024-07-09

申请号：US17578536

申请日：2022-01-19

Applicant: Japan Display Inc.

Inventor： Kenji Harada

IPC: H10K59/122 ,  H10K50/822

CPC classification number: H10K59/122 ,  H10K50/822

Abstract: According to one embodiment, a display device includes a base, a first insulating layer, first and second lower electrodes, a second insulating layer including a first opening, a second opening, and a first trench, an organic layer including a light-emitting layer and an upper electrode, and the first trench includes a bottom surface and first and second side surfaces, an interval between the first side surface and the second side surface in an upper portion of the first trench is smaller than that in the bottom surface, and the organic layer includes a first portion covering the first lower electrode, a second portion covering the second lower electrode and a third portion disposed on the bottom surface.

公开(公告)号：US12225806B2

公开(公告)日：2025-02-11

申请号：US17451502

申请日：2021-10-20

Applicant: Japan Display Inc.

Inventor： Sho Yanagisawa ,  Tetsuo Morita ,  Kenji Harada ,  Hiroshi Tabatake ,  Hideyuki Takahashi

IPC: H01L27/32 ,  H10K59/122 ,  H10K59/131 ,  H10K59/88

Abstract: According to one embodiment, a display device includes a substrate, first and second insulating layers, first and second pixel electrodes, first and second organic layers, first and second feed lines, first and second partitions, and a common electrode including first and second parts covering the first and second organic layers. The first organic layer is between the partitions. The second feed line and the second partition are located between the organic layers. The partitions are shaped such that a width of an upper part is greater than a width of a lower part. The first part is in contact with the first feed line between the first partition and the first organic layer.

公开(公告)号：US09905178B2

公开(公告)日：2018-02-27

申请号：US14190279

申请日：2014-02-26

Applicant: Japan Display Inc.

Inventor： Kenji Harada

IPC: G09G5/00 ,  G09G3/36

CPC classification number: G09G3/3655 ,  G09G2300/0426 ,  G09G2320/0233

Abstract: A row common electrode drive circuit and a column common electrode drive circuit control an effective value of a voltage to be applied to common electrodes along rows in which pixels are arrayed and an effective value of a voltage to be applied to the common electrodes along columns in which the pixels are arrayed.