公开(公告)号：US20190287468A1

公开(公告)日：2019-09-19

申请号：US16298581

申请日：2019-03-11

Applicant: Japan Display Inc.

Inventor： Yutaka MITSUZAWA

IPC: G09G3/36

Abstract: According to an aspect, a display device includes: a plurality of sub-pixels, each sub-pixel including at least one memory; a setting circuit configured to select either a first mode in which a still image is displayed or a second mode in which a moving image is displayed; and a switching circuit configured to switch coupling between the sub-pixels and the memories according to the selection made by the setting circuit. The first mode is a mode in which each of the sub-pixels is coupled to one of the at least one memory included in the sub-pixel, and the second mode is a mode including a time period in which at least one of the sub-pixels is coupled to the at least one memory included in another of the sub-pixels.

公开(公告)号：US20210210030A1

公开(公告)日：2021-07-08

申请号：US17175053

申请日：2021-02-12

Applicant: Japan Display Inc.

Inventor： Yutaka MITSUZAWA

IPC: G09G3/36

Abstract: According to an aspect, a display device includes: a plurality of sub-pixels, each sub-pixel including at least one memory; a setting circuit configured to select either a first mode in which a still image is displayed or a second mode in which a moving image is displayed; and a switching circuit configured to switch coupling between the sub-pixels and the memories according to the selection made by the setting circuit. The first mode is a mode in which each of the sub-pixels is coupled to one of the at least one memory included in the sub-pixel, and the second mode is a mode including a time period in which at least one of the sub-pixels is coupled to the at least one memory included in another of the sub-pixels.

公开(公告)号：US20190066634A1

公开(公告)日：2019-02-28

申请号：US16057934

申请日：2018-08-08

Applicant: Japan Display Inc.

Inventor： Masaya TAMAKI ,  Yutaka MITSUZAWA ,  Takayuki NAKAO ,  Yutaka OZAWA

IPC: G09G5/395 ,  G09G3/36

Abstract: A display device includes: sub-pixels each including a memory block including memories; memory selection line groups each including memory selection lines electrically coupled to the memory blocks in the sub-pixels that belong to the corresponding row; a memory selection circuit configured to concurrently output memory selection signals to the memory selection line groups; a potential line; a conduction switch provided for at least one memory in the memory block on a one-to-one basis; and an operating-memory conduction circuit configured to output, to the conduction switch, an operation signal for determining whether to electrically couple or uncouple the potential line and the corresponding one memory. Each memory is capable of storing sub-pixel data therein when being coupled to the potential line. Each sub-pixel displays an image based on the sub-pixel data stored in one memory in the sub-pixel according to the memory selection line supplied with the memory selection signal.

公开(公告)号：US20200152159A1

公开(公告)日：2020-05-14

申请号：US16738537

申请日：2020-01-09

Applicant: Japan Display Inc.

Inventor： Masaya TAMAKI ,  Yutaka MITSUZAWA ,  Takayuki NAKAO ,  Yutaka OZAWA

IPC: G09G5/395 ,  G09G3/36

Abstract: A display device includes: sub-pixels each including a memory block including memories; memory selection line groups each including memory selection lines electrically coupled to the memory blocks in the sub-pixels that belong to the corresponding row; a memory selection circuit configured to concurrently output memory selection signals to the memory selection line groups; a potential line; a conduction switch provided for at least one memory in the memory block on a one-to-one basis; and an operating-memory conduction circuit configured to output, to the conduction switch, an operation signal for determining whether to electrically couple or uncouple the potential line and the corresponding one memory. Each memory is capable of storing sub-pixel data therein when being coupled to the potential line. Each sub-pixel displays an image based on the sub-pixel data stored in one memory in the sub-pixel according to the memory selection line supplied with the memory selection signal.

公开(公告)号：US20200152147A1

公开(公告)日：2020-05-14

申请号：US16744638

申请日：2020-01-16

Applicant: Japan Display Inc.

Inventor： Yutaka MITSUZAWA ,  Takayuki NAKAO ,  Yutaka OZAWA ,  Masaya TAMAKI

IPC: G09G3/36

Abstract: A display device is provided and includes sub-pixels each including a sub-pixel electrode, and a first and second memory; a clock signal output circuit configured to, based on a reference clock signal, output a plurality of clock signals having different frequencies; a selection circuit configured to select one of the clock signals as a selected clock signal; a memory selection circuit configured to select all of the first memories included in all the sub-pixels or all of the second memories included in all the sub-pixels in synchronization with the selected clock signal; a common electrode facing all of the sub-pixel electrodes; and a common-electrode driving circuit configured to provide a common potential to the common electrode, wherein the common potential is inverted in synchronization with the reference clock signal, wherein the sub-pixel electrode is driven based on sub-pixel data stored in the selected one of the memories to display an image.

公开(公告)号：US20220005433A1

公开(公告)日：2022-01-06

申请号：US17480754

申请日：2021-09-21

Applicant: Japan Display Inc.

Inventor： Yutaka MITSUZAWA ,  Tatsuya ISHII

IPC: G09G3/36 ,  G09G3/00

Abstract: According to one embodiment, a display device including a plurality of pixels each of which includes a memory is provided. The display device includes a plurality of signal lines connected to the plurality of pixels, a signal line drive circuit configured to provide a data signal to one of the memories through one of the signal lines, a readout circuit configured to read the data signal in the memory through the signal line, and an output wire configured to externally output the data signal read by the readout circuit without passing through the signal line drive circuit.

公开(公告)号：US20190333460A1

公开(公告)日：2019-10-31

申请号：US16393533

申请日：2019-04-24

Applicant: Japan Display Inc.

Inventor： Yutaka MITSUZAWA

IPC: G09G3/36

Abstract: A display device includes: a display unit including pixels each including a holding circuit that holds a pixel signal; a driver that drives the pixels based on image signals and supply the pixel signal to the holding circuit of each pixel; an encoding circuit that encodes the image signals on a frame basis; storage that stores data resulting from encoding; a determination circuit that determines whether the image signals for consecutive frames are moving image signals or still image signals; and a controller that controls the driver based on the image signals and the result of the determination circuit. The controller brings the driver into a first state for driving the pixels based on the image signals when the result indicates the moving image signals, and into a second state for causing at least part of the driver to stop operating when the result indicates the still image signals.

公开(公告)号：US20190005904A1

公开(公告)日：2019-01-03

申请号：US16020055

申请日：2018-06-27

Applicant: Japan Display Inc.

Inventor： Yutaka MITSUZAWA ,  Takayuki NAKAO ,  Yutaka OZAWA ,  Masaya TAMAKI

IPC: G09G3/36

Abstract: A display device includes: a plurality of sub-pixels each including a memory block; a clock signal output circuit configured to output a plurality of clock signals having different frequencies; a selection circuit configured to select one of the clock signals as a selected clock signal; a plurality of memory selection line groups provided for respective rows; a memory selection circuit configured to output a memory selection signal concurrently to the memory selection line groups in synchronization with the selected clock signal, the memory selection signal being a signal for selecting one from a plurality of memories in each of the memory blocks; a common electrode to which a common potential common to the sub-pixels is supplied; and a common-electrode driving circuit configured to switch the common potential in synchronization with the reference clock signal and output the switched common potential.