公开(公告)号：US20190088688A1

公开(公告)日：2019-03-21

申请号：US16196269

申请日：2018-11-20

Applicant: Japan Display Inc.

Inventor： Koji YAMAMOTO ,  Tatsuya ISHII

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/02 ,  G09G3/3266 ,  G09G3/36

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

公开(公告)号：US20220173132A1

公开(公告)日：2022-06-02

申请号：US17671709

申请日：2022-02-15

Applicant: Japan Display Inc.

Inventor： Koji YAMAMOTO ,  Tatsuya ISHII

IPC: H01L27/12 ,  G09G3/36 ,  H01L29/786 ,  H01L27/02 ,  G09G3/3266

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

公开(公告)号：US20220157268A1

公开(公告)日：2022-05-19

申请号：US17525347

申请日：2021-11-12

Applicant: Japan Display Inc.

Inventor： Tatsuya ISHII

IPC: G09G3/36

Abstract: A display device includes a display unit including a plurality of pixels, a first drive circuit supplying a gate voltage to drive the plurality of pixels, a gate line connected to the plurality of pixels and the first drive circuit, the gate line transmitting the gate voltage to the plurality of pixels, a second drive circuit supplying a drive voltage corresponding to a luminance of each of the plurality of pixels, a data line connected to the plurality of pixels and the second drive circuit, the data line transmitting the drive voltage to the plurality of pixels, a back gate circuit generating a back gate voltage having a reverse polarity of the gate voltage, and a back gate line extending parallel to the gate line, the back gate line transmitting the back gate voltage to the plurality of pixels.

公开(公告)号：US20230123255A1

公开(公告)日：2023-04-20

申请号：US18085633

申请日：2022-12-21

Applicant: Japan Display Inc.

Inventor： Koji YAMAMOTO ,  Tatsuya ISHII

IPC: H01L27/12 ,  G09G3/36 ,  H01L29/786 ,  H01L27/02 ,  G09G3/3266

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

公开(公告)号：US20170033124A1

公开(公告)日：2017-02-02

申请号：US15201809

申请日：2016-07-05

Applicant: Japan Display Inc.

Inventor： Tatsuya ISHII

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1222 ,  H01L27/1248 ,  H01L29/78618 ,  H01L29/78645

Abstract: According to one embodiment, a semiconductor device includes first and second gate electrodes, a semiconductor layer, an output electrode, and an insulating layer. The semiconductor layer includes first source and drain areas, a first channel area facing the first gate electrode, second source and drain areas, and a second channel area facing the second gate electrode. The output electrode outputs voltage produced in the first and second drain areas. In the semiconductor device, the first drain area is in contact with the second drain area. The insulating layer includes a hole portion communicating with one of the first and second drain areas. The output electrode is in contact with one of the first and second drain areas via the hole portion.

Abstract translation: 根据一个实施例，半导体器件包括第一和第二栅电极，半导体层，输出电极和绝缘层。 半导体层包括第一源极和漏极区域，面对第一栅极电极的第一沟道区域，第二源极和漏极区域以及面对第二栅极电极的第二沟道区域。 输出电极输出在第一和第二漏极区域产生的电压。 在半导体器件中，第一漏极区域与第二漏极区域接触。 绝缘层包括与第一和第二漏极区域中的一个连通的孔部分。 输出电极经由孔部分与第一和第二漏极区域中的一个接触。

公开(公告)号：US20150301378A1

公开(公告)日：2015-10-22

申请号：US14688356

申请日：2015-04-16

Applicant: Japan Display Inc.

Inventor： Tatsuya ISHII ,  Tetsuya IIZUKA

IPC: G02F1/1368 ,  G02F1/1333 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/786

CPC classification number: G02F1/136209 ,  H01L27/1222 ,  H01L27/124 ,  H01L29/78621 ,  H01L29/78633 ,  H01L29/78645 ,  H01L29/78675

Abstract: A display device includes an insulating substrate, a semiconductor layer formed of polycrystalline silicon, including a first impurity area, a second impurity area, and a channel area, an insulating film which covers the semiconductor layer, a gate electrode formed on the insulating film and opposed to the channel area, a source line electrically connected to the first impurity area, an electrode electrically connected to the second impurity area, and a light-shielding film located between the insulating substrate and the semiconductor layer, disposed at a position displaced from a position opposed to the source line, and opposed to an area including a boundary between the channel area and the second impurity area.

Abstract translation: 显示装置包括绝缘基板，由多晶硅形成的半导体层，包括第一杂质区域，第二杂质区域和沟道区域，覆盖半导体层的绝缘膜，形成在绝缘膜上的栅电极和 与沟道区相对的源极线，与第一杂质区电连接的电源线，与第二杂质区电连接的电极，以及位于绝缘基板与半导体层之间的遮光膜， 与源极线相对的位置，并且与包括沟道区域和第二杂质区域之间的边界的区域相对。

公开(公告)号：US20210210036A1

公开(公告)日：2021-07-08

申请号：US17212576

申请日：2021-03-25

Applicant: Japan Display Inc.

Inventor： Tatsuya ISHII

IPC: G09G3/36

Abstract: According to an aspect, a display device includes a plurality of sub-pixels. Each of the sub-pixels includes a memory block including a memory configured to store therein sub-pixel data and a sub-pixel electrode coupled to the memory block. The memory includes first and second transistors configured to store therein the sub-pixel data in accordance with an electrical charge of a floating gate, the first and second transistors include respective drains that are coupled to each other, and a coupling point of the drains is coupled to a node. The sub-pixel electrode is coupled to the node, and each of the sub-pixels is configured to display an image based on a potential of the node.

公开(公告)号：US20200243573A1

公开(公告)日：2020-07-30

申请号：US16851663

申请日：2020-04-17

Applicant: Japan Display Inc.

Inventor： Koji YAMAMOTO ,  Tatsuya ISHII

IPC: H01L27/12 ,  G09G3/36 ,  H01L29/786 ,  H01L27/02 ,  G09G3/3266

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

公开(公告)号：US20200006398A1

公开(公告)日：2020-01-02

申请号：US16558850

申请日：2019-09-03

Applicant: Japan Display Inc.

Inventor： Koji YAMAMOTO ,  Tatsuya ISHII

IPC: H01L27/12 ,  G09G3/36 ,  G09G3/3266 ,  H01L27/02 ,  H01L29/786

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

公开(公告)号：US20180197893A1

公开(公告)日：2018-07-12

申请号：US15912672

申请日：2018-03-06

Applicant: Japan Display Inc.

Inventor： Koji YAMAMOTO ,  Tatsuya ISHII

IPC: H01L27/12 ,  G09G3/36 ,  H01L29/786 ,  H01L27/02 ,  G09G3/3266

CPC classification number: H01L27/1244 ,  G09G3/3266 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3696 ,  G09G2310/0286 ,  G09G2330/04 ,  H01L27/0255 ,  H01L29/78633 ,  H01L29/78648

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.