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1.发明授权Apparatus and method for representing gated-clock latches for phase abstraction 有权用于表示相位抽取的门控锁存器的装置和方法公开(公告)号：US06745377B2
公开(公告)日：2004-06-01
申请号：US10116584
申请日：2002-04-04
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： An apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs is provided. With the apparatus and method, latches are “colored,” i.e. classified into different types, based on information obtained from a clock tree of the circuit design. Clock tree primitives contain sufficient information to taxonomize the clocks into their respective phases and identify which latches are gated latches. In coloring the latches, gated latches are replaced in the circuit design with a free running clock, a multiplexor, and a sequence of L1 to Ln latches to provide a feedback path via the data path. This allows the gated latch to be phase abstracted without losing the “gated” functionality of the gated latch in the resulting trace. Once the latches are colored in this way, phase abstraction is performed on the colored circuit design. The phase abstracted netlist is then subjected to verification and a trace is produced. The coloring information of the original circuit, plus information as to the exact nature of the phase abstraction performed, is then used to transform the phase abstracted trace to one which resembles a trace of the circuit without phase abstraction.
摘要翻译： 提供了一种用于自动使用相位抽象以用于电路设计的增强验证的装置和方法。 利用该装置和方法，锁存器是“彩色的”，即根据从电路设计的时钟树获得的信息被分类成不同类型。 时钟树原语包含足够的信息，将时钟分类到各自的相位，并确定哪些锁存器是门控锁存器。 在对锁存器进行着色时，门控锁存器在电路设计中被替换为具有自由运行时钟，多路复用器和L1到Ln锁存器的序列，以通过数据路径提供反馈路径。 这允许门控锁存器被相位抽取，而不会损失所得到的跟踪中门控锁存器的“选通”功能。 一旦锁存器以这种方式着色，相位抽象就在彩色电路设计上执行。 然后对相抽象网表进行验证，并生成跟踪。 原始电路的着色信息，以及执行相位抽象的确切性质的信息，然后用于将相位抽象曲线转换为类似于没有相位抽象的电路轨迹。
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2.发明授权Apparatus and method for removing effects of phase abstraction from a phase abstracted trace 有权从相位抽象曲线去除相位抽象效应的装置和方法公开(公告)号：US06748573B2
公开(公告)日：2004-06-08
申请号：US10116583
申请日：2002-04-04
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： An apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs is provided. With the apparatus and method, latches are “colored,” i.e. classified into different types, based on information obtained from a clock tree of the circuit design. Clock tree primitives contain sufficient information to taxonomize the clocks into their respective phases and identify which latches are gated latches. In coloring the latches, gated latches are replaced in the circuit design with a free running clock, a multiplexor, and a sequence of L1 to Ln latches to provide a feedback path via the data path. This allows the gated latch to be phase abstracted without losing the “gated” functionality of the gated latch in the resulting trace. Once the latches are colored in this way, phase abstraction is performed on the colored circuit design. The phase abstracted netlist is then subjected to verification and a trace is produced. The coloring information of the original circuit, plus information as to the exact nature of the phase abstraction performed, is then used to transform the phase abstracted trace to one which resembles a trace of the circuit without phase abstraction.
摘要翻译： 提供了一种用于自动使用相位抽象以用于电路设计的增强验证的装置和方法。 利用该装置和方法，锁存器是“彩色的”，即根据从电路设计的时钟树获得的信息被分类成不同类型。 时钟树原语包含足够的信息，将时钟分类到各自的相位，并确定哪些锁存器是门控锁存器。 在对锁存器进行着色时，门控锁存器在电路设计中被替换为具有自由运行时钟，多路复用器和L1到Ln锁存器的序列，以通过数据路径提供反馈路径。 这允许门控锁存器被相位抽取，而不会损失所得到的跟踪中门控锁存器的“选通”功能。 一旦锁存器以这种方式着色，相位抽象就在彩色电路设计上执行。 然后对相抽象网表进行验证，并生成跟踪。 原始电路的着色信息，以及执行相位抽象的确切性质的信息，然后用于将相位抽象曲线转换为类似于没有相位抽象的电路轨迹。
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3.发明授权Apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs 有权自动使用相位抽象以增强电路设计验证的装置和方法公开(公告)号：US06763505B2
公开(公告)日：2004-07-13
申请号：US10116607
申请日：2002-04-04
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： An apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs is provided. With the apparatus and method, latches are “colored,” i.e. classified into different types, based on information obtained from a clock tree of the circuit design. Clock tree primitives contain sufficient information to taxonomize the clocks into their respective phases and identify which latches are gated latches. In coloring the latches, gated latches are replaced in the circuit design with a free running clock, a multiplexor, and a sequence of L1 to Ln latches to provide a feedback path via the data path. This allows the gated latch to be phase abstracted without losing the “gated” functionality of the gated latch in the resulting trace. Once the latches are colored in this way, phase abstraction is performed on the colored circuit design. The phase abstracted netlist is then subjected to verification and a trace is produced. The coloring information of the original circuit, plus information as to the exact nature of the phase abstraction performed, is then used to transform the phase abstracted trace to one which resembles a trace of the circuit without phase abstraction.
摘要翻译： 提供了一种用于自动使用相位抽象以用于电路设计的增强验证的装置和方法。 利用该装置和方法，锁存器是“彩色的”，即根据从电路设计的时钟树获得的信息被分类成不同类型。 时钟树原语包含足够的信息，将时钟分类到各自的相位，并确定哪些锁存器是门控锁存器。 在对锁存器进行着色时，门控锁存器在电路设计中被替换为具有自由运行时钟，多路复用器和L1到Ln锁存器的序列，以通过数据路径提供反馈路径。 这允许门控锁存器被相位抽取，而不会损失所得到的跟踪中门控锁存器的“选通”功能。 一旦锁存器以这种方式着色，相位抽象就在彩色电路设计上执行。 然后对相抽象网表进行验证，并生成跟踪。 原始电路的着色信息，以及执行相位抽象的确切性质的信息，然后用于将相位抽象曲线转换为类似于没有相位抽象的电路轨迹。
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公开(公告)号：US07093218B2
公开(公告)日：2006-08-15
申请号：US10782673
申请日：2004-02-19
CPC分类号： G06F17/5022
摘要： A design verification system includes a first verification engine to model the operation of a first design of an integrated circuit to obtain verification results including the model's adherence to a property during N time steps of its operation, proofs that one or more verification targets can be reached, and verification coverage results for targets that are not reached. A correspondence engine determines the functional correspondence between the first design and a second design of the integrated circuit. Functional correspondence, if demonstrated, enables reuse of the first engine's verification results to reduce resources expended during subsequent analysis of the second design. The correspondence determination may be simplified using a composite model of the integrated circuit having “implies” logic in lieu of “EXOR” logic. The implies logic indicates conditions in which a node in the second design achieves a state that is contrary to the verification results for the first design.
摘要翻译： 设计验证系统包括第一验证引擎，用于建模集成电路的第一设计的操作，以获得包括模型在其操作的N个时间步骤期间对属性的遵守性的验证结果，证明可以达到一个或多个验证目标 ，以及未达到的目标的验证覆盖率结果。 通信引擎确定集成电路的第一设计和第二设计之间的功能对应关系。 如果证明功能对应关系，则能够重新使用第一引擎的验证结果，以减少后续第二次设计分析中花费的资源。 可以使用具有“暗示”逻辑的集成电路的复合模型来代替“EXOR”逻辑来简化对应确定。 意味着逻辑表示第二设计中的节点达到与第一设计的验证结果相反的状态的条件。
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5.发明授权Method and system for reduction of XOR/XNOR subexpressions in structural design representations 有权在结构设计表示中减少XOR / XNOR子表达式的方法和系统公开(公告)号：US07831937B2
公开(公告)日：2010-11-09
申请号：US11955112
申请日：2007-12-12
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.
摘要翻译： 公开了一种用于在结构设计表示中减少XOR / XNOR子表达式的方法，系统和计算机程序产品。 该方法包括接收初始设计，其中初始设计表示包含XOR门的电子电路。 从一组适用的简化模式中选择用于初始设计的第一简化模式，其中第一简化模式是XOR / XNOR简化模式，并且根据第一简化模式执行简化初始设计以生成缩减 设计包含减少数量的异或门。 确定缩减设计的尺寸是否小于初始设计的尺寸，并且响应于确定减小的设计的尺寸小于初始设计的尺寸，初始设计被替换为 减少设计。
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6.发明授权Method and system for reduction of and/or subexpressions in structural design representations 失效在结构设计表示中减少和/或次表达的方法和系统公开(公告)号：US07380221B2
公开(公告)日：2008-05-27
申请号：US11086721
申请日：2005-03-22
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from a set of applicable simplification modes is selected, wherein said simplification mode is an AND/OR simplification mode, and a simplification of the initial design according to the first simplification mode is performed to generate a reduced design. Whether a size of the reduced design is less than a size of the initial design is determined and, in response to determining that the size of the reduced design is less than the size of the initial design, the initial design is replaced with the reduced design.
摘要翻译： 公开了一种用于减少包含AND和OR门的结构设计表示中的子表达式的方法，系统和计算机程序产品。 该方法包括接收初始设计，其中初始设计表示包含与门的电子电路。 选择用于从一组适用的简化模式进行初始设计的第一简化模式，其中所述简化模式是AND / OR简化模式，并且执行根据第一简化模式的初始设计的简化以生成缩减设计 。 确定减小设计的尺寸是否小于初始设计的尺寸，并且响应于确定减小的设计的尺寸小于初始设计的尺寸，初始设计被替换为简化的设计 。
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7.发明授权Method and system for reduction of AND/OR subexpressions in structural design representations 有权减少结构设计表示中的AND / OR子表达式的方法和系统公开(公告)号：US07882459B2
公开(公告)日：2011-02-01
申请号：US11944668
申请日：2007-11-26
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from a set of applicable simplification modes is selected, wherein said simplification mode is an AND/OR simplification mode, and a simplification of the initial design according to the first simplification mode is performed to generate a reduced design. Whether a size of the reduced design is less than a size of the initial design is determined and, in response to determining that the size of the reduced design is less than the size of the initial design, the initial design is replaced with the reduced design.
摘要翻译： 公开了一种用于减少包含AND和OR门的结构设计表示中的子表达式的方法，系统和计算机程序产品。 该方法包括接收初始设计，其中初始设计表示包含与门的电子电路。 选择用于从一组适用的简化模式进行初始设计的第一简化模式，其中所述简化模式是AND / OR简化模式，并且执行根据第一简化模式的初始设计的简化以生成缩减设计 。 确定减小设计的尺寸是否小于初始设计的尺寸，并且响应于确定减小的设计的尺寸小于初始设计的尺寸，初始设计被替换为简化的设计 。
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8.发明授权公开(公告)号：US07509605B2
公开(公告)日：2009-03-24
申请号：US11301112
申请日：2005-12-12
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint net where the modified constraint net is FALSE for all cycles after any cycle in which the original constraint is FALSE. The method may include, instead of eliminating constraints, determining that the verification result is a target-not-asserted result and that the second netlist constraints are a superset of the first netlist constraints or that the verification result is a target-asserted result and that the first netlist constraints are a superset of the second netlist constraints. In either case, the method may include creating the composite netlist by importing all of the original constraints into the composite netlist.
摘要翻译： 增量验证方法包括消除来自第一网表的验证约束并且使用所得到的网表来创建适合于确定设计的第一网表与第二网表之间的等价性的无约束复合网表。 从网表中消除约束可以包括在原始约束为FALSE的任何周期之后添加修改的约束网络，其中修改的约束网络对于所有周期是假的。 该方法可以包括，而不是消除约束，确定验证结果是目标未被断言的结果，并且第二网表约束是第一网表约束的超集，或者验证结果是目标断言结果， 第一个网表约束是第二个网表限制的超集。 在任一情况下，该方法可以包括通过将所有原始约束导入到复合网表中来创建复合网表。
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9.发明授权Method and system for enhanced verification through structural target decomposition 失效通过结构目标分解增强验证的方法和系统公开(公告)号：US07350169B2
公开(公告)日：2008-03-25
申请号：US11143330
申请日：2005-06-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/504
摘要： A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, wherein the design includes a first target set and a first register set including one or more registers. A structural product extraction is formed from one or more targets from the first target set and the structural product extraction is recursed for one or more next-state functions of a subset of the one or more registers. A sum-of-products form is recursed from the structural product extraction for one or more next-state functions of a subset of the one or more registers and a product-of-sums form of a result of the second recursing is decomposed to generate a decomposition of the product-of-sums form. The decomposition of the product-of-sums form is synthesized into a second target set and a subset of the second target set to recursively decompose is chosen. In response to the subset of the second target set being nonempty, the first target set is recursively decomposed and, in response to the second target set being empty, verification is applied to the second target set.
摘要翻译： 公开了一种用于执行电子设计验证的方法，系统和计算机程序产品。 该方法包括接收设计，其中该设计包括第一目标组和包括一个或多个寄存器的第一寄存器组。 从第一目标集合的一个或多个目标形成结构性产品提取，并且针对一个或多个寄存器的子集的一个或多个下一个状态函数递归结构乘积提取。 从一个或多个寄存器的子集的一个或多个下一个状态函数的结构产品提取中递归产生积和形式，并且将第二次递归的结果的乘积形式分解生成 产品总和形式的分解。 求和形式的分解被合成为第二目标集合，并且选择第二目标集合的递归分解的子集。 响应于第二目标集合的子集是非空的，第一目标集被递归地分解，并且响应于第二目标集合为空，将验证应用于第二目标集合。
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10.发明授权Method and system for enhanced verification through binary decision diagram-based target decomposition 有权通过基于二进制决策图的目标分解来增强验证的方法和系统公开(公告)号：US07343573B2
公开(公告)日：2008-03-11
申请号：US11143331
申请日：2005-06-02
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is generated. A recursive extraction of one or more next states of selected registers is generated using the binary decision diagram analysis of the first target set and the primary input set. The recursive extraction is decomposed to generate a second target set, and the second target set is verified.
摘要翻译： 公开了一种用于执行电子设计验证的方法，系统和计算机程序产品。 该方法包括接收包括第一目标组，主要输入集和包括一个或多个寄存器的第一寄存器组的设计。 生成设计的二进制决策图分析。 使用第一目标集合和主要输入集合的二进制判定图分析来生成所选寄存器的一个或多个下一个状态的递归提取。 递归提取被分解以产生第二目标集合，并且验证第二目标集合。
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