公开(公告)号：US07962705B2

公开(公告)日：2011-06-14

申请号：US12729227

申请日：2010-03-22

申请人： Herman Schmit ,  Andrew Caldwell ,  Brad Hutchings ,  Jason Redgrave ,  Steven Teig

发明人： Herman Schmit ,  Andrew Caldwell ,  Brad Hutchings ,  Jason Redgrave ,  Steven Teig

IPC分类号： G06F9/315

CPC分类号： H03K19/17736 ,  H03K19/1776

摘要： Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

摘要翻译： 一些实施例提供了一种呈现比物理存储器更窄和更深的虚拟存储器的方法。 该方法接收包括一组实际存储器地址位和一组虚拟存储器位置位的存储器地址位置。 该方法使用实际存储器地址位从物理存储器中检索原始存储器字。 该方法通过使用桶形移位器将原始存储器字移动由虚拟存储器位置位确定的量，创建移位的存储器字。 该方法读取移位的存储器字的一部分。

公开(公告)号：US07587698B1

公开(公告)日：2009-09-08

申请号：US11751629

申请日：2007-05-21

申请人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

发明人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

IPC分类号： G06F17/50 ,  H03K19/00 ,  H03K19/177

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17776

摘要： Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.

摘要翻译： 一些实施例提供可重构集成电路（“IC”）。 该IC具有几个可重新配置电路，每个具有几个配置周期的配置。 可重新配置的电路包括几个延时可重构电路。 在IC的操作期间，每个特定的时间延长的可重新配置电路在至少两个连续周期内保持其配置中的至少一个，以便允许信号传播通过包含特定延时电路的信号路径， 在期望的时间内。

公开(公告)号：US07236009B1

公开(公告)日：2007-06-26

申请号：US11082200

申请日：2005-03-15

申请人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

发明人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F7/38 ,  H01L25/00

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17776

摘要： Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.

摘要翻译： 一些实施例提供可重构集成电路（“IC”）。 该IC具有几个可重新配置电路，每个具有几个配置周期的配置。 可重新配置的电路包括几个延时可重构电路。 在IC的操作期间，每个特定的时间延长的可重新配置电路在至少两个连续周期内保持其配置中的至少一个，以便允许信号传播通过包含特定延时电路的信号路径， 在期望的时间内。

公开(公告)号：US07898291B2

公开(公告)日：2011-03-01

申请号：US12534841

申请日：2009-08-03

申请人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

发明人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

IPC分类号： H03K19/173

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17776

摘要： Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit. The method then maintains a configuration of the particular reconfigurable circuit constant over at least two contiguous reconfiguration cycles in order to reduce signal delay through the signal path and thereby satisfy the timing constraint.

摘要翻译： 一些实施例提供可重构集成电路（“IC”）。 该IC具有几个可重新配置电路，每个具有几个配置周期的配置。 可重新配置的电路包括几个延时可重构电路。 在IC的操作期间，每个特定的时间延长的可重新配置电路在至少两个连续周期内保持其配置中的至少一个，以便允许信号传播通过包含特定延时电路的信号路径， 在期望的时间内。 一些实施例提供了一种设计可重配置IC的方法，该可重配置IC具有若干可重构电路，每个可重新配置电路具有若干配置并在几个重新配置周期中操作。 该方法识别通过IC的不符合定时约束的信号路径。 信号路径包括几个电路，其中之一是特定的可重新配置电路。 该方法然后在至少两个连续的重新配置周期上保持特定可重新配置电路的配置不变，以减少通过信号路径的信号延迟，从而满足定时约束。

公开(公告)号：US20100241800A1

公开(公告)日：2010-09-23

申请号：US12729227

申请日：2010-03-22

申请人： Herman Schmit ,  Andrew Caldwell ,  Brad Hutchings ,  Jason Redgrave ,  Steven Teig

发明人： Herman Schmit ,  Andrew Caldwell ,  Brad Hutchings ,  Jason Redgrave ,  Steven Teig

IPC分类号： G06F12/00 ,  G06F9/315

CPC分类号： H03K19/17736 ,  H03K19/1776

摘要： Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

摘要翻译： 一些实施例提供了一种呈现比物理存储器更窄和更深的虚拟存储器的方法。 该方法接收包括一组实际存储器地址位和一组虚拟存储器位置位的存储器地址位置。 该方法使用实际存储器地址位从物理存储器中检索原始存储器字。 该方法通过使用桶形移位器将原始存储器字移动由虚拟存储器位置位确定的量，创建移位的存储器字。 该方法读取移位的存储器字的一部分。

公开(公告)号：US07694083B1

公开(公告)日：2010-04-06

申请号：US11371352

申请日：2006-03-08

申请人： Herman Schmit ,  Andrew Caldwell ,  Brad Hutchings ,  Jason Redgrave ,  Steven Teig

发明人： Herman Schmit ,  Andrew Caldwell ,  Brad Hutchings ,  Jason Redgrave ,  Steven Teig

IPC分类号： G06F9/315

CPC分类号： H03K19/17736 ,  H03K19/1776

摘要： Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

摘要翻译： 一些实施例提供了一种呈现比物理存储器更窄和更深的虚拟存储器的方法。 该方法接收包括一组实际存储器地址位和一组虚拟存储器位置位的存储器地址位置。 该方法使用实际存储器地址位从物理存储器中检索原始存储器字。 该方法通过使用桶形移位器将原始存储器字移动由虚拟存储器位置位确定的量，创建移位的存储器字。 该方法读取移位的存储器字的一部分。

公开(公告)号：US20100066407A1

公开(公告)日：2010-03-18

申请号：US12534841

申请日：2009-08-03

申请人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

发明人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

IPC分类号： H03K19/173 ,  G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17776

摘要： Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit. The method then maintains a configuration of the particular reconfigurable circuit constant over at least two contiguous reconfiguration cycles in order to reduce signal delay through the signal path and thereby satisfy the timing constraint.

摘要翻译： 一些实施例提供可重构集成电路（“IC”）。 该IC具有几个可重新配置电路，每个具有几个配置周期的配置。 可重新配置的电路包括几个延时可重构电路。 在IC的操作期间，每个特定的时间延长的可重新配置电路在至少两个连续周期内保持其配置中的至少一个，以便允许信号传播通过包含特定延时电路的信号路径， 在期望的时间内。 一些实施例提供了一种设计可重配置IC的方法，该可重配置IC具有若干可重构电路，每个可重新配置电路具有若干配置并在几个重新配置周期中操作。 该方法识别通过IC的不符合定时约束的信号路径。 信号路径包括几个电路，其中之一是特定的可重新配置电路。 该方法然后在至少两个连续的重新配置周期上保持特定可重新配置电路的配置不变，以减少通过信号路径的信号延迟，从而满足定时约束。

公开(公告)号：US20120098568A1

公开(公告)日：2012-04-26

申请号：US13344581

申请日：2012-01-05

申请人： Jason Redgrave ,  Andrew Caldwell ,  Steven Teig

发明人： Jason Redgrave ,  Andrew Caldwell ,  Steven Teig

IPC分类号： H03K19/173

CPC分类号： G06F17/504 ,  H03K19/1733

摘要： Some embodiments provide a method of performing a mathematical operation on a set of operands. The mathematical operation includes several sub-operations. The method examines several bits of at least one operand at a time and depending on the value of these bits, reconfigures a single logic circuit to perform one of the sub-operations to generate a partial result of the mathematical operation. In some embodiments, the logic circuit is reconfigured by receiving a first set of configuration data that cause the logic circuit to reconfigure to perform a first sub-operation operation and a second set of configuration data that cause the logic circuit to reconfigure to perform a second sub-operation. In some embodiments, the logic circuit receives different inputs based on the value of the bits being examined. In some embodiments, the mathematical operation is multiplication and the sub-operations are addition and subtraction.

摘要翻译： 一些实施例提供了对一组操作数执行数学运算的方法。 数学运算包括几个子操作。 该方法一次检查至少一个操作数的几位，并且根据这些位的值，重新配置单个逻辑电路以执行子操作之一以产生数学运算的部分结果。 在一些实施例中，通过接收第一组配置数据来重新配置逻辑电路，所述第一组配置数据使逻辑电路重新配置以执行第一子操作操作和第二组配置数据，使得逻辑电路重新配置以执行第二 子操作。 在一些实施例中，逻辑电路基于所检查的位的值来接收不同的输入。 在一些实施例中，数学运算是乘法运算，子运算是加法和减法运算。

公开(公告)号：US07535252B1

公开(公告)日：2009-05-19

申请号：US11754263

申请日：2007-05-25

申请人： Steven Teig ,  Andrew Caldwell ,  Jason Redgrave

发明人： Steven Teig ,  Andrew Caldwell ,  Jason Redgrave

IPC分类号： H03K19/173

CPC分类号： G06F17/504 ,  H03K19/1733

摘要： Some embodiments provide a method of operating a configurable circuit. The method performs a first operation by the configurable circuit based on a first configuration data set. When a user-design signal has a value from a set of values, the method performs a second operation based on a second configuration data set, after the first operation. When the user-design signal does not have a value from said set of values, the method performs a third operation based on a third configuration data set, after the first operation. Some embodiments provide a reconfigurable IC that includes a set of reconfigurable circuits and sets of associated configuration storage elements that store configuration data sets. At least one reconfigurable circuit receives a first sub-set of its configuration data when a user-design signal has a first value and receives a second sub-set of its configuration data when the user-design signal has a second value.

摘要翻译： 一些实施例提供了一种操作可配置电路的方法。 该方法基于第一配置数据集执行可配置电路的第一操作。 当用户设计信号具有来自一组值的值时，该方法在第一操作之后基于第二配置数据集执行第二操作。 当用户设计信号不具有来自所述一组值的值时，该方法在第一操作之后基于第三配置数据集执行第三操作。 一些实施例提供了可重新配置的IC，其包括一组可重构电路和存储配置数据集的关联配置存储元件的集合。 当用户设计信号具有第一值时，至少一个可重构电路接收其配置数据的第一子集，并且当用户设计信号具有第二值时接收其配置数据的第二子集。

公开(公告)号：US08664974B2

公开(公告)日：2014-03-04

申请号：US13011840

申请日：2011-01-21

申请人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

发明人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

IPC分类号： H03K19/173 ,  H01L25/00 ,  G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17776

摘要： A reconfigurable integrated circuit (“IC”) that has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.

摘要翻译： 具有几个可重新配置电路的可重构集成电路（“IC”），每个可配置电路在几个配置周期中具有多种配置。 可重新配置的电路包括几个延时可重构电路。 在IC的操作期间，每个特定的时间延长的可重新配置电路在至少两个连续周期内保持其配置中的至少一个，以便允许信号传播通过包含特定延时电路的信号路径， 在期望的时间内。