公开(公告)号：US08629692B1

公开(公告)日：2014-01-14

申请号：US13536638

申请日：2012-06-28

申请人： Jayarama Ubaradka ,  Dharmaray M. Nedalgi

发明人： Jayarama Ubaradka ,  Dharmaray M. Nedalgi

IPC分类号： H03K19/0175

CPC分类号： H03K3/356104

摘要： State definition and retention circuits are described. In one embodiment, a circuit includes two cross-connected PMOS transistors, first, second, and third NMOS transistors coupled to the PMOS transistors, an inverter circuit, and an output transistor connected to the PMOS transistors and to an output terminal of the circuit. The second NMOS transistor is connected to an input terminal of the circuit. A drain terminal and a gate terminal of the third NMOS transistor are connected to gate terminals of the PMOS transistors. The inverter circuit is coupled to the first and second NMOS transistors and to the input terminal. The inverter circuit is connected between a first power supply and a first base voltage. The PMOS transistors, the NMOS transistors, and the output transistor are connected between a second power supply and a second base voltage. Other embodiments are also described.

摘要翻译： 描述状态定义和保持电路。 在一个实施例中，电路包括两个交叉连接的PMOS晶体管，耦合到PMOS晶体管的第一，第二和第三NMOS晶体管，反相器电路和连接到PMOS晶体管和输出端的输出晶体管。 第二NMOS晶体管连接到电路的输入端。 第三NMOS晶体管的漏极端子和栅极端子连接到PMOS晶体管的栅极端子。 逆变器电路耦合到第一和第二NMOS晶体管和输入端。 逆变器电路连接在第一电源和第一基极电压之间。 PMOS晶体管，NMOS晶体管和输出晶体管连接在第二电源和第二基极之间。 还描述了其它实施例。

公开(公告)号：US08283947B1

公开(公告)日：2012-10-09

申请号：US13152764

申请日：2011-06-03

申请人： Jayarama Ubaradka ,  Dharmaray M. Nedalgi

发明人： Jayarama Ubaradka ,  Dharmaray M. Nedalgi

IPC分类号： H03K19/0175

CPC分类号： H03K19/00315 ,  H03K19/018521

摘要： A high voltage tolerant bus holder circuit and method of operating the bus holder circuit utilizes first and second control transistors connected in parallel between a control terminal of a pull-up transistor and a bus. The first control transistor is used to turn on the pull-up transistor during a pull-up mode of operation. The second control transistor is used to turn off the pull-down transistor when a voltage on the bus exceeds a threshold.

摘要翻译： 高耐压总线保持器电路和操作总线保持器电路的方法利用并联连接在上拉晶体管的控制端和总线之间的第一和第二控制晶体管。 第一控制晶体管用于在上拉操作模式期间导通上拉晶体管。 当总线上的电压超过阈值时，第二控制晶体管用于关断下拉晶体管。

公开(公告)号：US20110006810A1

公开(公告)日：2011-01-13

申请号：US12866734

申请日：2009-02-02

申请人： Dharmaray M. Nedalgi

发明人： Dharmaray M. Nedalgi

IPC分类号： H03K19/0175

CPC分类号： H03K19/0013 ,  H03K19/018521

摘要： The invention relates to a CMOS input circuit for receiving low-swing input signals, which is an alternative to the CMOS input circuits as known from the prior art. The CMOS input circuit according to the invention comprises a leveling circuit (LC) that is constructed for arranging, under control of a voltage associated with an output voltage of a CMOS input stage (Inv1), a leveling transistor (M3) which is located in a supply path of the CMOS input stage (Inv1), (i) as a forward-biased diode-connected transistor for regulating the voltage on a source of the CMOS input stage (Inv1) for reducing the gate-source voltage of a switching transistor (M1, M2) in the CMOS input stage (Inv1), when an input voltage of the CMOS input circuit assumes a level associated with a first logical level causing the switching transistor (M1, M2) to be switched off, and (ii) as a conductive path when the input voltage assumes a level associated with a second logical level causing the switching transistor (M1, M2) to be switched on. The invention also relates to an Input-Output circuit, an electronic circuit and a semiconductor device comprising such CMOS input circuit. The invention provides an alternative to known CMOS input circuit that make use of a diode-connected transistor that is short-circuited in case of one of the input voltage levels. An advantageous embodiment of the invention incorporates a positive feedback mechanism that makes the circuit more suitable for low supply voltages.

摘要翻译： 本发明涉及用于接收低摆幅输入信号的CMOS输入电路，其是现有技术中已知的CMOS输入电路的替代方案。 根据本发明的CMOS输入电路包括调平电路（LC），其被构造用于在与CMOS输入级（Inv1）的输出电压相关联的电压的控制下布置调平电路（M3），调平晶体管 CMOS输入级（Inv1）的供给路径，（i）作为用于调节CMOS输入级（Inv1）的源极上的电压的正向偏置二极管连接晶体管，用于降低开关晶体管的栅极 - 源极电压 （M1，M2）在CMOS输入级（Inv1）中的输入电压（M1，M2），当CMOS输入电路的输入电压为与关闭开关晶体管（M1，M2）的第一逻辑电平相关联的电平时，（ii） 当输入电压采取与第二逻辑电平相关联的电平，导致开关晶体管（M1，M2）被接通时作为导电路径。 本发明还涉及一种输入输出电路，电子电路和包括这种CMOS输入电路的半导体器件。 本发明提供了一种已知的CMOS输入电路的替代方案，其利用在其中一个输入电压电平的情况下短路的二极管连接的晶体管。 本发明的有利实施例包括正反馈机制，其使电路更适合于低电源电压。

公开(公告)号：US20100085080A1

公开(公告)日：2010-04-08

申请号：US12532201

申请日：2008-03-26

申请人： Dharmaray M. Nedalgi

发明人： Dharmaray M. Nedalgi

IPC分类号： H03K19/0185

CPC分类号： H03K19/018521

摘要： An electronic device is provided with a high-voltage tolerant circuit. The high-voltage tolerant circuit comprises an input terminal for receiving an input signal (VIN), a first node (A) and a second node (B), wherein the second node (B) is coupled to an input of a receiver (R). The high-voltage tolerant circuit furthermore comprises a first NMOS transistor (N1) and a first PMOS transistor (P1) coupled in parallel between the input terminal and the second node (B). Furthermore, a second PMOS transistor (P2) is coupled between the input terminal and node A and a second NMOS transistor is coupled with one of its terminals to the first node. The gate of the first NMOS transistor (N2) is coupled to a supply voltage (VDDE). The gate of the first PMOS transistor (P1) is coupled to the first node (A). The gate of the second NMOS transistor (N2) and the gate of the second PMOS transistor (P2) are coupled to the supply voltage (VDDE).

摘要翻译： 电子设备具有高耐压电路。 高耐压电路包括用于接收输入信号（VIN），第一节点（A）和第二节点（B）的输入端，其中第二节点（B）耦合到接收器（R ）。 高耐压电路还包括并联在输入端和第二节点（B）之间的第一NMOS晶体管（N1）和第一PMOS晶体管（P1）。 此外，第二PMOS晶体管（P2）耦合在输入端子和节点A之间，第二NMOS晶体管与其一个端子耦合到第一节点。 第一NMOS晶体管（N2）的栅极耦合到电源电压（VDDE）。 第一PMOS晶体管（P1）的栅极耦合到第一节点（A）。 第二NMOS晶体管（N2）的栅极和第二PMOS晶体管（P2）的栅极耦合到电源电压（VDDE）。

公开(公告)号：US20090261860A1

公开(公告)日：2009-10-22

申请号：US12297004

申请日：2007-04-11

申请人： Dharmaray M. Nedalgi

发明人： Dharmaray M. Nedalgi

IPC分类号： H03K19/0185

CPC分类号： H03K19/018521 ,  H03K3/356113 ,  H03K19/00315

摘要： An electronic circuit is provided comprising an input (VIN) for coupling a circuit of a first voltage domain to the electronic circuit, and a first, second, third and fourth transistor coupled between a supply voltage (VDD) and a voltage (VSS). The third transistor (M1) is coupled between the voltage (VSS) and a first node (tn). The second transistor (M2) is coupled between a second node (tp) and the output (VOUT). The third transistor (M3) is coupled between the first node (tn) and the output (VOUT). The fourth transistor (M4) is coupled between the supply voltage (VDD) and the second node (tp). A first reference voltage generating unit (RC) receives the voltage at the first node (tn) and the voltage (VSS) as input, and its output is coupled to the gate of the second transistor (M2). A second reference voltage generating unit (RD) receives the supply voltage (VDD) and the voltage of the second node (tp) as input, and its output is coupled to the gate of the third transistor (M3). The first and second reference voltage generating units (RD, RC) generate a reference voltage according to at least one of the logic states of the first, second, third or fourth transistor (M1-M4).

摘要翻译： 提供一种电子电路，其包括用于将第一电压域的电路耦合到电子电路的输入端（VIN）以及耦合在电源电压（VDD）和电压（VSS）之间的第一，第二，第三和第四晶体管。 第三晶体管（M1）耦合在电压（VSS）和第一节点（tn）之间。 第二晶体管（M2）耦合在第二节点（tp）和输出端（VOUT）之间。 第三晶体管（M3）耦合在第一节点（tn）和输出端（VOUT）之间。 第四晶体管（M4）耦合在电源电压（VDD）和第二节点（tp）之间。 第一参考电压产生单元（RC）接收第一节点（tn）处的电压和电压（VSS）作为输入，并且其输出耦合到第二晶体管（M2）的栅极。 第二参考电压产生单元（RD）接收电源电压（VDD）和第二节点（tp）的电压作为输入，并且其输出耦合到第三晶体管（M3）的栅极。 第一和第二参考电压产生单元（RD，RC）根据第一，第二，第三或第四晶体管（M1-M4）的至少一个逻辑状态产生参考电压。

公开(公告)号：US08330491B2

公开(公告)日：2012-12-11

申请号：US12532201

申请日：2008-03-26

申请人： Dharmaray M. Nedalgi

发明人： Dharmaray M. Nedalgi

IPC分类号： H03K19/0175 ,  H03K19/20 ,  H03K19/094 ,  H03K3/00 ,  H03K5/08 ,  H03B1/00

CPC分类号： H03K19/018521

摘要： An electronic device is provided with a high-voltage tolerant circuit. The high-voltage tolerant circuit comprises an input terminal for receiving an input signal (VIN), a first node (A) and a second node (B), wherein the second node (B) is coupled to an input of a receiver (R). The high-voltage tolerant circuit furthermore comprises a first NMOS transistor (N1) and a first PMOS transistor (P1) coupled in parallel between the input terminal and the second node(B). Furthermore, a second PMOS transistor (P2) is coupled between the input terminal and node A and a second NMOS transistor is coupled with one of its terminals to the first node. The gate of the first NMOS transistor (N2) is coupled to a supply voltage (VDDE). The gate of the first PMOS transistor (P1) is coupled to the first node (A). The gate of the second NMOS transistor (N2) and the gate of the second PMOS transistor (P2) are coupled to the supply voltage (VDDE).

摘要翻译： 电子设备具有高耐压电路。 高耐压电路包括用于接收输入信号（VIN），第一节点（A）和第二节点（B）的输入端，其中第二节点（B）耦合到接收器（R ）。 高耐压电路还包括并联在输入端和第二节点（B）之间的第一NMOS晶体管（N1）和第一PMOS晶体管（P1）。 此外，第二PMOS晶体管（P2）耦合在输入端子和节点A之间，第二NMOS晶体管与其一个端子耦合到第一节点。 第一NMOS晶体管（N2）的栅极耦合到电源电压（VDDE）。 第一PMOS晶体管（P1）的栅极耦合到第一节点（A）。 第二NMOS晶体管（N2）的栅极和第二PMOS晶体管（P2）的栅极耦合到电源电压（VDDE）。

公开(公告)号：US07741874B2

公开(公告)日：2010-06-22

申请号：US12297004

申请日：2007-04-11

申请人： Dharmaray M. Nedalgi

发明人： Dharmaray M. Nedalgi

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521 ,  H03K3/356113 ,  H03K19/00315

摘要： An electronic circuit is provided comprising an input (VIN) for coupling a circuit of a first voltage domain to the electronic circuit, and a first, second, third and fourth transistor coupled between a supply voltage (VDD) and a voltage (VSS). The third transistor (M1) is coupled between the voltage (VSS) and a first node (tn). The second transistor (M2) is coupled between a second node (tp) and the output (VOUT). The third transistor (M3) is coupled between the first node (tn) and the output (VOUT). The fourth transistor (M4) is coupled between the supply voltage (VDD) and the second node (tp). A first reference voltage generating unit (RC) receives the voltage at the first node (tn) and the voltage (VSS) as input, and its output is coupled to the gate of the second transistor (M2). A second reference voltage generating unit (RD) receives the supply voltage (VDD) and the voltage of the second node (tp) as input, and its output is coupled to the gate of the third transistor (M3). The first and second reference voltage generating units (RD, RC) generate a reference voltage according to at least one of the logic states of the first, second, third or fourth transistor (M1-M4).

摘要翻译： 提供一种电子电路，其包括用于将第一电压域的电路耦合到电子电路的输入端（VIN）以及耦合在电源电压（VDD）和电压（VSS）之间的第一，第二，第三和第四晶体管。 第三晶体管（M1）耦合在电压（VSS）和第一节点（tn）之间。 第二晶体管（M2）耦合在第二节点（tp）和输出端（VOUT）之间。 第三晶体管（M3）耦合在第一节点（tn）和输出端（VOUT）之间。 第四晶体管（M4）耦合在电源电压（VDD）和第二节点（tp）之间。 第一参考电压产生单元（RC）接收第一节点（tn）处的电压和电压（VSS）作为输入，并且其输出耦合到第二晶体管（M2）的栅极。 第二参考电压产生单元（RD）接收电源电压（VDD）和第二节点（tp）的电压作为输入，并且其输出耦合到第三晶体管（M3）的栅极。 第一和第二参考电压产生单元（RD，RC）根据第一，第二，第三或第四晶体管（M1-M4）的至少一个逻辑状态产生参考电压。

公开(公告)号：US20090189643A1

公开(公告)日：2009-07-30

申请号：US12343012

申请日：2008-12-23

申请人： Dharmaray M. Nedalgi

发明人： Dharmaray M. Nedalgi

IPC分类号： H03K19/20 ,  H03K19/094 ,  H03K19/003

CPC分类号： G05F3/24

摘要： A constant voltage generator device provides a first and a second transistor having their main current path coupled serially via a common terminal for providing a constant output voltage at the common terminal of said transistors. The device provides one or more potential dividers having a plurality of serially connected resistive elements. A first voltage is obtained from a first combination of resistive elements of the potential divider and a second voltage obtained from a second combination of resistive elements of the potential divider. The first and the second voltages are supplied to the first and the second voltage at the control terminals of the first and the second transistors, respectively.

摘要翻译： 恒压发生器装置提供第一和第二晶体管，其主电流路径经由公共端串联连接，用于在所述晶体管的公共端提供恒定的输出电压。 该器件提供具有多个串联连接的电阻元件的一个或多个电位分压器。 从分压器的电阻元件的第一组合和从分压器的电阻元件的第二组合获得的第二电压获得第一电压。 第一和第二电压分别被提供给第一和第二晶体管的控制端的第一和第二电压。