公开(公告)号：US20220393672A1

公开(公告)日：2022-12-08

申请号：US17889892

申请日：2022-08-17

申请人： Jayen Desai ,  Gerald Pasdast ,  Peipei Wang ,  Debendra Das Sharma

发明人： Jayen Desai ,  Gerald Pasdast ,  Peipei Wang ,  Debendra Das Sharma

IPC分类号： H03K5/13 ,  G06F1/12

摘要： Embodiments herein relate to a clock interpolation system. The system may be configured to identify, at a change in logical state of a recovered clock signal, a logical state of a first signal when the first signal is delayed by a delay value. The system may be further configured to identify, at a change in logical state of a second signal, a logical state of the clock signal when the clock signal is delayed by the delay value. Based on the two identifications, the delay value and/or a timing of the clock signal may be adjusted. Other embodiments may be described and/or claimed.

公开(公告)号：US20070013395A1

公开(公告)日：2007-01-18

申请号：US11166825

申请日：2005-06-24

申请人： Jayen Desai ,  James Dewey ,  David Purvis

发明人： Jayen Desai ,  James Dewey ,  David Purvis

IPC分类号： G01R31/02

CPC分类号： G01R31/2853

摘要： One exemplary device has a plurality of leads with termination impedances, and a standard impedance. Among the termination impedances are master impedances arranged to be calibrated by comparison with the standard impedance and slave impedances arranged to be calibrated in accordance with an associated master impedance.

摘要翻译： 一个示例性器件具有多个具有端接阻抗的引线和标准阻抗。 在终端阻抗中，主阻抗被布置为通过与根据相关联的主阻抗被校准的标准阻抗和从阻抗比较来校准。

公开(公告)号：US20070064848A1

公开(公告)日：2007-03-22

申请号：US11232154

申请日：2005-09-21

申请人： Jayen Desai

发明人： Jayen Desai

IPC分类号： H04L7/00 ,  H04L7/02

CPC分类号： H04L7/033 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025

摘要： A method and apparatus of recovering a clock signal from an input data signal consistent with certain embodiments, where the clock signal has a clock cycle equal to one data bit period, involves identifying an earliest transition time position in a sequence of data signal transitions; identifying a latest transition time position in the sequence of data signal transitions; calculating an approximate average transition time of the sequence of clock transitions; calculating a sampling time for sampling data in the input data signal as the approximate average transition time plus one half clock cycle; and adjusting a sampling clock time to approximate the sampling time. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

摘要翻译： 一种从输入数据信号恢复时钟信号的方法和装置，其与时钟信号具有等于一个数据位周期的时钟周期的某些实施例相关，包括识别数据信号转换序列中最早的转换时间位置; 识别数据信号转换序列中的最新转换时间位置; 计算时钟转换序列的近似平均过渡时间; 计算用于在输入数据信号中采样数据的采样时间作为近似平均过渡时间加上一个半个时钟周期; 并调整采样时钟时间以近似采样时间。 该摘要不被认为是限制性的，因为其他实施例可能偏离本摘要中描述的特征。

公开(公告)号：US07873132B2

公开(公告)日：2011-01-18

申请号：US11232154

申请日：2005-09-21

申请人： Jayen Desai

发明人： Jayen Desai

IPC分类号： H03D3/24

CPC分类号： H04L7/033 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025

摘要： A method and apparatus of recovering a clock signal from an input data signal consistent with certain embodiments, where the clock signal has a clock cycle equal to one data bit period, involves identifying an earliest transition time position in a sequence of data signal transitions; identifying a latest transition time position in the sequence of data signal transitions; calculating an approximate average transition time of the sequence of clock transitions; calculating a sampling time for sampling data in the input data signal as the approximate average transition time plus one half clock cycle; and adjusting a sampling clock time to approximate the sampling time. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

摘要翻译： 一种从输入数据信号恢复时钟信号的方法和装置，其与时钟信号具有等于一个数据位周期的时钟周期的某些实施例相关，包括识别数据信号转换序列中最早的转换时间位置; 识别数据信号转换序列中的最新转换时间位置; 计算时钟转换序列的近似平均过渡时间; 计算用于在输入数据信号中采样数据的采样时间作为近似平均过渡时间加上一个半个时钟周期; 并调整采样时钟时间以近似采样时间。 该摘要不被认为是限制性的，因为其他实施例可能偏离本摘要中描述的特征。

公开(公告)号：US20060091925A1

公开(公告)日：2006-05-04

申请号：US10978328

申请日：2004-11-01

申请人： Jayen Desai ,  Bruce Doyle

发明人： Jayen Desai ,  Bruce Doyle

IPC分类号： H03K5/13

CPC分类号： H04L7/033 ,  H04L7/0025

摘要： Embodiments of an interpolator system and method are disclosed. One embodiment of an interpolator system, among others, includes an interpolator having first and second output terminals providing output signals; a comparator coupled to the first and second output terminals and configured to detect a peak voltage level of the output signals and compare the peak voltage level with a reference voltage level; and an impedance element coupled to the comparator and the first and second output terminals, wherein the comparator is configured to provide a control signal to the impedance element to change the impedance of the impedance element to set a voltage variation of the output signals.

摘要翻译： 公开了一种内插器系统和方法的实施例。 内插器系统的一个实施例包括具有提供输出信号的第一和第二输出端的内插器; 比较器，耦合到第一和第二输出端，并被配置为检测输出信号的峰值电压电平，并将峰值电压电平与参考电压电平进行比较; 以及耦合到所述比较器和所述第一和第二输出端子的阻抗元件，其中所述比较器被配置为向所述阻抗元件提供控制信号以改变所述阻抗元件的阻抗以设置所述输出信号的电压变化。

公开(公告)号：US20070096789A1

公开(公告)日：2007-05-03

申请号：US11261337

申请日：2005-10-28

申请人： Jayen Desai ,  Samuel Naffziger

发明人： Jayen Desai ,  Samuel Naffziger

IPC分类号： G06F1/04

CPC分类号： G06F1/04 ,  H03L7/07 ,  H03L7/081 ,  H03L7/0814

摘要： A method of generating a clock signal using a digital frequency synthesizer includes providing a base clock to the digital frequency synthesizer, comparing a phase of an output clock from the digital frequency synthesizer with a phase of a reference signal, and issuing at least one frequency control command to the digital frequency synthesizer to align the phases.

公开(公告)号：US20060168483A1

公开(公告)日：2006-07-27

申请号：US11041821

申请日：2005-01-24

申请人： Derek Sherlock ,  Jayen Desai ,  Chih-Jen Chen

发明人： Derek Sherlock ,  Jayen Desai ,  Chih-Jen Chen

IPC分类号： G06F11/00

CPC分类号： G01R31/31858

摘要： Systems, methodologies, media, and other embodiments associated with validating a bus are described. One exemplary system embodiment includes an integrated circuit operably connectable to a bus, the bus being connectable to an external device configured to drive one or more electrical signals onto the bus. The integrated circuit may comprise a first logic configured to receive a test sequence of electrical signals from the bus, a second logic configured to produce a check sequence of electrical signals related to the test sequence of electrical signals, and a compare logic operably connected to the first logic and the second logic. The compare logic may be configured to determine whether the bus is correctly transmitting data based, at least in part, on comparing the test sequence and the check sequence.