公开(公告)号：US06434650B1

公开(公告)日：2002-08-13

申请号：US09176571

申请日：1998-10-21

申请人： Jeff C. Morris ,  Robert J. Greiner ,  Narayana S. Iyer ,  Pranav H. Mehta ,  Shreekant Thakkar ,  Peter Ruscito

发明人： Jeff C. Morris ,  Robert J. Greiner ,  Narayana S. Iyer ,  Pranav H. Mehta ,  Shreekant Thakkar ,  Peter Ruscito

IPC分类号： G06F1300

CPC分类号： G06F13/4291

摘要： An apparatus and method for communication between a host CPU and a security co-processor are disclosed, in which a bus having a bi-directional data and command bus, a bi-directional control line, and a uni-directional clock line, is coupled to the CPU and to the co-processor. The bus supports data transfer between the CPU and the co-processor, including read operations and write operations, where each such operation includes a command phase, a data transfer phase, and an error check phase. The CPU and the co-processor have a dual master slave mode wherein either may be master of the bus, while the other is the slave. The bi-directional data and command bus carries command information from the master to the slave 10 during the command phase, and carries data from the master to the slave during the data transfer phase for a write operation, and from the slave to the master for a read operation. The bi-directional control line specifies the start and end of each transfer. The uni-directional clock line synchronously clocks both the bi-directional data and command bus and the bi-directional control line. Data is transferred a packet at a time; each packet consists of an octet of data, which 15 is transferred during 8 clocks. Flow control need only be applied once for each packet of data, and thus, only once per 8 clocks.

摘要翻译： 公开了一种用于主机CPU和安全协处理器之间通信的装置和方法，其中具有双向数据和命令总线，双向控制线和单向时钟线的总线被耦合 到CPU和协处理器。 总线支持CPU和协处理器之间的数据传输，包括读操作和写操作，其中每个这样的操作包括命令阶段，数据传输阶段和错误校验阶段。 CPU和协处理器具有双主从模式，其中也可以是总线的主机，而另一个是从机。 双向数据和命令总线在命令阶段将命令信息从主机传送到从机10，并在写操作的数据传输阶段将数据从主机传送到从机，从从机到主机， 一个读操作。 双向控制线指定每次传输的开始和结束。 单向时钟线同时对双向数据和命令总线以及双向控制线进行时钟同步。 数据一次传送一个数据包; 每个数据包由八位字节的数据组成，在8个时钟周期内传输15个数据。 流量控制只需对每个数据包应用一次，因此每8个时钟只需一次。

公开(公告)号：US06895504B1

公开(公告)日：2005-05-17

申请号：US09676068

申请日：2000-09-29

申请人： Minda Zhang ,  Pranav H. Mehta

发明人： Minda Zhang ,  Pranav H. Mehta

IPC分类号： H04L9/08 ,  H04N7/16 ,  H04N7/167 ,  H04L9/00

CPC分类号： H04N21/4143 ,  H04L9/0869 ,  H04L9/0891 ,  H04L2209/12 ,  H04L2209/601 ,  H04N7/165 ,  H04N7/1675 ,  H04N21/42684 ,  H04N21/63345

摘要： A unique processor serial number may be utilized to augment a device key seed stored in a non-volatile memory. In this way, a relatively secure system may be enabled that facilitates renewing the device key. An integrated circuit may include a transport demultiplexer and key logic. The key logic communicates with the processor using a secure protocol. The key logic can generate random numbers that may be hashed with the processor serial number and the device key seed to generate a device key. The device key may be provided to a head end to facilitate secure communications between the head end and the client.

摘要翻译： 可以使用唯一的处理器序列号来增加存储在非易失性存储器中的设备密钥种子。 以这种方式，可以启用有利于更新设备密钥的相对安全的系统。 集成电路可以包括传输解复用器和密钥逻辑。 关键逻辑使用安全协议与处理器进行通信。 关键逻辑可以生成可以使用处理器序列号和设备密钥种子来散列的随机数，以生成设备密钥。 设备密钥可以被提供给头端以便于头端和客户端之间的安全通信。

公开(公告)号：US06392712B1

公开(公告)日：2002-05-21

申请号：US09540694

申请日：2000-03-31

申请人： Paul S. Gryskiewicz ,  Pranav H. Mehta

发明人： Paul S. Gryskiewicz ,  Pranav H. Mehta

IPC分类号： H04N974

CPC分类号： H04N7/0806 ,  H04N5/073 ,  H04N7/012

摘要： An interlaced video signal may be combined with a progressive video signal, such as a graphics signal, by converting the interlaced video signal into a progressive signal. A new frame of the converted progressive signal is constructed from each field of the interlaced signal. The graphics signal is interlaced, then combined with the converted progressive signal. The combined signals may then be transmitted to a display, such as a television set. The interlaced video signal, which is transmitted at twice its incoming speed, remains temporally correct so that operations, such as scaling and 3:2 pulldown, may be performed with minimal resulting artifacts. The small amount of memory used to combine the signals may be embedded in the receiver circuitry.

摘要翻译： 通过将隔行扫描视频信号转换成逐行信号，隔行视频信号可以与逐行视频信号（诸如图形信号）组合。 由交错信号的每个场构成转换的逐行信号的新帧。 图形信号被隔行扫描，然后与转换的逐行信号组合。 然后，组合的信号可以被发送到诸如电视机的显示器。 以两倍的传入速度传输的隔行扫描视频信号在时间上保持正确，从而可以以最小的产生的伪影来执行诸如缩放和3：2下拉的操作。 用于组合信号的少量存储器可以嵌入在接收器电路中。