公开(公告)号：US07430578B2

公开(公告)日：2008-09-30

申请号：US10610831

申请日：2003-06-30

Applicant: Eric Debes ,  William W. Macy ,  Jonathan J. Tyler ,  James Coke ,  Frank Binns ,  Scott Rodgers ,  Peter Ruscito ,  Bret Toll ,  Vesselin Naydenov ,  Masood Tahir ,  David Jackson

Inventor： Eric Debes ,  William W. Macy ,  Jonathan J. Tyler ,  James Coke ,  Frank Binns ,  Scott Rodgers ,  Peter Ruscito ,  Bret Toll ,  Vesselin Naydenov ,  Masood Tahir ,  David Jackson

IPC: G06F7/38

CPC classification number: G06F9/3885 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F17/147 ,  G06F17/15

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. The processor performs operations on data elements in said first packed byte data and said second packed byte data to generate a third packed data in response to receiving an instruction. A plurality of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data.

Abstract translation: 一种用于在处理器中包括用于对压缩字节数据执行乘法运算的指令的方法和装置。 在一个实施例中，处理器耦合到存储器。 存储器中存储有第一打包字节数据和第二打包字节数据。 处理器对所述第一打包字节数据和所述第二打包字节数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。 该第三打包数据中的多个数据元素存储对第一和第二打包字节数据中的数据元素执行加法运算的结果。

公开(公告)号：US06434650B1

公开(公告)日：2002-08-13

申请号：US09176571

申请日：1998-10-21

Applicant: Jeff C. Morris ,  Robert J. Greiner ,  Narayana S. Iyer ,  Pranav H. Mehta ,  Shreekant Thakkar ,  Peter Ruscito

Inventor： Jeff C. Morris ,  Robert J. Greiner ,  Narayana S. Iyer ,  Pranav H. Mehta ,  Shreekant Thakkar ,  Peter Ruscito

IPC: G06F1300

CPC classification number: G06F13/4291

Abstract: An apparatus and method for communication between a host CPU and a security co-processor are disclosed, in which a bus having a bi-directional data and command bus, a bi-directional control line, and a uni-directional clock line, is coupled to the CPU and to the co-processor. The bus supports data transfer between the CPU and the co-processor, including read operations and write operations, where each such operation includes a command phase, a data transfer phase, and an error check phase. The CPU and the co-processor have a dual master slave mode wherein either may be master of the bus, while the other is the slave. The bi-directional data and command bus carries command information from the master to the slave 10 during the command phase, and carries data from the master to the slave during the data transfer phase for a write operation, and from the slave to the master for a read operation. The bi-directional control line specifies the start and end of each transfer. The uni-directional clock line synchronously clocks both the bi-directional data and command bus and the bi-directional control line. Data is transferred a packet at a time; each packet consists of an octet of data, which 15 is transferred during 8 clocks. Flow control need only be applied once for each packet of data, and thus, only once per 8 clocks.

Abstract translation: 公开了一种用于主机CPU和安全协处理器之间通信的装置和方法，其中具有双向数据和命令总线，双向控制线和单向时钟线的总线被耦合 到CPU和协处理器。 总线支持CPU和协处理器之间的数据传输，包括读操作和写操作，其中每个这样的操作包括命令阶段，数据传输阶段和错误校验阶段。 CPU和协处理器具有双主从模式，其中也可以是总线的主机，而另一个是从机。 双向数据和命令总线在命令阶段将命令信息从主机传送到从机10，并在写操作的数据传输阶段将数据从主机传送到从机，从从机到主机， 一个读操作。 双向控制线指定每次传输的开始和结束。 单向时钟线同时对双向数据和命令总线以及双向控制线进行时钟同步。 数据一次传送一个数据包; 每个数据包由八位字节的数据组成，在8个时钟周期内传输15个数据。 流量控制只需对每个数据包应用一次，因此每8个时钟只需一次。