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1.发明授权System and method for transfer of data between processors using a locked set, head and tail pointers 失效使用锁定集，头和尾指针在处理器之间传输数据的系统和方法公开(公告)号：US07355601B2
公开(公告)日：2008-04-08
申请号：US11303525
申请日：2005-12-16
申请人： Jeffrey A. Andrews , Nicholas R. Baker , J. Andrew Goossen , Russell D. Hoover , Eric O. Mejdrich , Sandra S. Woodward
发明人： Jeffrey A. Andrews , Nicholas R. Baker , J. Andrew Goossen , Russell D. Hoover , Eric O. Mejdrich , Sandra S. Woodward
IPC分类号： G06F12/08 , G06F9/46 , G06F13/20 , G06F15/80 , G06F13/28 , G09G9/36 , G06T15/00 , G06F15/16 , G06F15/78
CPC分类号： G06T15/005
摘要： A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data.
摘要翻译： CPU模块包括被配置为执行高级主机相关任务的主机元件，以及被配置为执行与高级主机相关任务相关联的数据生成任务的一个或多个数据生成处理元件。 每个数据生成处理元件包括被配置为接收输入数据的逻辑和被配置为处理输入数据以产生输出数据的逻辑。
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公开(公告)号：US07475190B2
公开(公告)日：2009-01-06
申请号：US10961752
申请日：2004-10-08
IPC分类号： G06F15/167 , G06F12/00
CPC分类号： G06F12/126 , G06F12/084 , G06F2212/2515
摘要： Methods for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a lock set mode by the processor in which it resides. While in the lock set mode, this portion of the cache may be accessed directly by another processor without lengthy “backing” writes of the accessed data to main memory.
摘要翻译： 提供了一种方法，用于通过另一处理器快速访问位于一个处理器的高速缓存中的数据，同时避免长时间访问主存储器。 高速缓存的一部分可以由其驻留的处理器置于锁定模式中。 在锁定模式下，高速缓存的这一部分可能被另一个处理器直接访问，而不会对所访问的数据进行长时间的“后退”写入主存储器。
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3.发明授权公开(公告)号：US07577794B2
公开(公告)日：2009-08-18
申请号：US10961751
申请日：2004-10-08
IPC分类号： G06F12/00
CPC分类号： G06F12/0828
摘要： Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the remote device and processor that satisfy a set of associated coherency rules.
摘要翻译： 提供了用于减少由远程设备访问驻留在处理器的高速缓存中的数据所涉及的等待时间量的方法和装置。 对于一些实施例，虚拟信道可以用于在满足一组相关联的一致性规则的远程设备和处理器之间进行请求/响应事务。
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公开(公告)号：US20090077320A1
公开(公告)日：2009-03-19
申请号：US12274548
申请日：2008-11-20
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/084 , G06F2212/2515
摘要： Apparatus and system for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a lock set mode by the processor in which it resides. While in the lock set mode, this portion of the cache may be accessed directly by another processor without lengthy “backing” writes of the accessed data to main memory.
摘要翻译： 提供了用于通过另一处理器快速访问位于一个处理器的高速缓存中的数据的装置和系统，同时避免对主存储器的长时间访问。 高速缓存的一部分可以由其驻留的处理器置于锁定模式中。 在锁定模式下，高速缓存的这一部分可能被另一个处理器直接访问，而不会对所访问的数据进行长时间的“后退”写入主存储器。
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5.发明授权公开(公告)号：US07305524B2
公开(公告)日：2007-12-04
申请号：US10961749
申请日：2004-10-08
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F12/0822 , G06F2212/302
摘要： Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.
摘要翻译： 提供了可用于维护由处理器和远程设备访问的数据的一致性的方法和装置。 远程设备可以利用各种机制，诸如远程高速缓存目录，转储缓冲区和/或未完成的事务缓冲器来跟踪可以保存由远程设备发起的请求所针对的数据的处理器高速缓存行的状态。 基于这些机制的内容，针对不在处理器高速缓存中的数据的请求可以直接路由到存储器，从而减少总体延迟。
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公开(公告)号：US08020168B2
公开(公告)日：2011-09-13
申请号：US12117897
申请日：2008-05-09
CPC分类号： G06F15/17356 , G06F15/7825
摘要： A NOC for dynamic virtual software pipelining including IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including: a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, each stage assigned to a thread of execution on an IP block; and each stage executing on a thread of execution on an IP block, including a first stage executing on an IP block, producing output data and sending by the first stage the produced output data to a second stage, the output data including control information for the next stage and payload data; and the second stage consuming the produced output data in dependence upon the control information.
摘要翻译： 一种用于动态虚拟软件流水线的NOC，包括IP块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，NOC还包括：计算机软件应用程序分段 每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段分配给IP块上的执行线程; 并且每个阶段在IP块上执行的执行线程，包括在IP块上执行的第一阶段，产生输出数据，并且通过第一阶段将产生的输出数据发送到第二阶段，所述输出数据包括用于 下一阶段和有效载荷数据; 并且第二阶段根据控制信息消耗所产生的输出数据。
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公开(公告)号：US20090282222A1
公开(公告)日：2009-11-12
申请号：US12117897
申请日：2008-05-09
IPC分类号： G06F9/30
CPC分类号： G06F15/17356 , G06F15/7825
摘要： A NOC for dynamic virtual software pipelining including IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including: a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, each stage assigned to a thread of execution on an IP block; and each stage executing on a thread of execution on an IP block, including a first stage executing on an IP block, producing output data and sending by the first stage the produced output data to a second stage, the output data including control information for the next stage and payload data; and the second stage consuming the produced output data in dependence upon the control information.
摘要翻译： 一种用于动态虚拟软件流水线的NOC，包括IP块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，NOC还包括：计算机软件应用程序分段 每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段分配给IP块上的执行线程; 并且每个阶段在IP块上执行的执行线程，包括在IP块上执行的第一阶段，产生输出数据，并且通过第一阶段将产生的输出数据发送到第二阶段，所述输出数据包括用于 下一阶段和有效载荷数据; 并且第二阶段根据控制信息消耗所产生的输出数据。
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公开(公告)号：US20090138567A1
公开(公告)日：2009-05-28
申请号：US12102038
申请日：2008-04-14
IPC分类号： G06F15/167
CPC分类号： G06F15/16
摘要： A design structure embodied in a machine readable medium is provided. Embodiments of the design structure include a network on chip (‘NOC’), the NOC comprising: integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers; the network organized into partitions, each partition including at least one IP block, each partition assigned exclusive access to a separate physical memory address space; and one or more applications executing on one or more of the partitions.
摘要翻译： 提供体现在机器可读介质中的设计结构。 该设计结构的实施例包括片上网络（NOC），NOC包括：集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器适配于路由器 通信控制器和网络接口控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及每个网络接口控制器通过路由器控制IP间块通信; 网络组织成分区，每个分区包括至少一个IP块，每个分区分配独占访问单独的物理内存地址空间; 以及在一个或多个分区上执行的一个或多个应用程序。
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公开(公告)号：US20090109996A1
公开(公告)日：2009-04-30
申请号：US11926212
申请日：2007-10-29
IPC分类号： H04L12/66
CPC分类号： H04L45/00
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器， 其中每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器的IP间块通信的每个网络接口控制器。
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公开(公告)号：US08332592B2
公开(公告)日：2012-12-11
申请号：US10961750
申请日：2004-10-08
IPC分类号： G06F12/02
CPC分类号： G06F12/0831
摘要： Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. The remote device may include coherency logic, referred to herein as a snoop filter, designed to filter memory access requests that do not require bus commands to be sent to the processor. The snoop filter may filter requests based on a remote cache directory designed to mirror the processor cache directory, such that only those requests that target cache lines indicated to be valid in the processor cache result in snoop commands sent to the processor. Other requests (targeting data that is not cached in the processor) may be routed directly to memory without the latency conventionally associated with snoop requests.
摘要翻译： 提供了可用于维护由处理器和远程设备访问的数据的一致性的方法和装置。 远程设备可以包括相关性逻辑，这里称为窥探过滤器，被设计为过滤不需要将总线命令发送到处理器的存储器访问请求。 窥探过滤器可以基于旨在镜像处理器高速缓存目录的远程高速缓存目录来过滤请求，使得仅指示在处理器高速缓存中指示为有效的缓存行的那些请求导致发送到处理器的窥探命令。 其他请求（目标数据不被缓存在处理器中）可以直接路由到存储器，而不需要通常与侦听请求相关联的延迟。
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