公开(公告)号：US06356494B2

公开(公告)日：2002-03-12

申请号：US09751455

申请日：2001-01-02

申请人： Ji Eun Jang ,  Mi Young Kim ,  Jae Jin Lee

发明人： Ji Eun Jang ,  Mi Young Kim ,  Jae Jin Lee

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/1078

摘要： The present invention discloses an automatic precharge apparatus of a semiconductor memory device. An object of the present invention is to perform a sable precharge operation unrelated to change of the clock frequency by controlling to perform an precharge operation after constant delay time, regardless of an external clock signal. The automatic precharge apparatus of a semiconductor memory device comprises an automatic precharge signal generating unit receiving external control signals and then generating an internal precharge command signal, and outputting an automatic precharge signal by using the internal precharge command signal and control signals being related to a bust operation, a ras precharge signal generating unit for generating a ras precharge signal by receiving the automatic precharge signal, a delay unit for outputting a write recovery signal with a constant delay time, which is disabled in the reading operation and only enabled in the writing operation, when an internal precharge command signal is inputted, a ras generating unit for generating a ras signal without a delay time when inputting an external precharge command signal, whereas after a constant delay time in response to the write recovery signal when inputting the ras precharge signal.

摘要翻译： 本发明公开了一种半导体存储装置的自动预充电装置。 本发明的目的是通过控制在恒定的延迟时间之后执行预充电操作，而不管外部时钟信号如何，执行与时钟频率变化无关的可切换预充电操作。 半导体存储器件的自动预充电装置包括自动预充电信号发生单元，其接收外部控制信号，然后产生内部预充电命令信号，并且通过使用内部预充电命令信号和与胸部相关的控制信号输出自动预充电信号 ras预充电信号产生单元，用于通过接收自动预充电信号产生ras预充电信号;延迟单元，用于输出具有恒定延迟时间的写恢复信号，该读恢复信号在读操作中被禁止，并且仅在写操作中有效 当输入内部预充电命令信号时，在输入外部预充电命令信号时产生ras信号而没有延迟时间的ras产生单元，而在输入ras预充电信号时响应于写恢复信号的恒定延迟时间 。

公开(公告)号：US07126411B2

公开(公告)日：2006-10-24

申请号：US10999593

申请日：2004-11-30

申请人： Ji Eun Jang ,  Jae Jin Lee

发明人： Ji Eun Jang ,  Jae Jin Lee

IPC分类号： G05F1/10

CPC分类号： H03K17/302 ,  G11C5/145 ,  H02M3/07

摘要： Disclosed is a high voltage generator comprising: a first voltage level detector for detecting a voltage level of the high voltage; a second voltage level detector for detecting difference between the high voltage and a power supply voltage; a high voltage pump for performing a pumping operation to generate a high voltage when one of output signals of the first voltage level detector and the second voltage level detector is enabled; and a controller for receiving the output signal of the second voltage level detector, and for connecting a terminal through which the high voltage is output with the power supply voltage when the high voltage is lower than the power supply voltage.

公开(公告)号：US06765406B2

公开(公告)日：2004-07-20

申请号：US10330821

申请日：2002-12-27

申请人： Ji Eun Jang ,  Jae Jin Lee

发明人： Ji Eun Jang ,  Jae Jin Lee

IPC分类号： H03K19003

CPC分类号： H05K1/0246 ,  G11C7/10 ,  G11C11/4093 ,  H03K19/0175 ,  H05K1/0286 ,  H05K1/14 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/10022

摘要： A circuit board configured to provide multiple interfaces is disclosed. The circuit board comprises a termination slot inserted with a termination module configured to modulate circuits by applying a termination resistance and a termination voltage. If the termination module is inserted into the termination slot, the circuit board operates as a series stub terminated transceiver logic (SSTL) interface. Otherwise, the board operates as a low voltage transistor logic (LVTTL) interface. Additionally, the board comprises a switch configured to selectively connect a termination resistance to a bus. If the switch connects the termination resistance to the bus, the board operates as an SSTL interface. Otherwise, the board operates as an LVTTL interface.

摘要翻译： 公开了一种被配置为提供多个接口的电路板。 电路板包括插入有终端模块的终端插槽，其配置成通过施加终端电阻和终止电压来调制电路。 如果终端模块插入终端插槽，则电路板作为串行存根终端收发器逻辑（SSTL）接口运行。 否则，该板作为低电压晶体管逻辑（LVTTL）接口工作。 另外，电路板包括被配置为选择性地将终端电阻连接到总线的开关。 如果开关将终端电阻连接到总线，则该板作为SSTL接口工作。 否则，该板作为LVTTL接口运行。

公开(公告)号：US06819134B2

公开(公告)日：2004-11-16

申请号：US10331287

申请日：2002-12-30

申请人： Ji Eun Jang

发明人： Ji Eun Jang

IPC分类号： H03K1900

CPC分类号： G11C8/10 ,  G11C29/006 ,  G11C29/20 ,  G11C2029/1802

摘要： A decoding circuit for a wafer burn-in test internally generates a strobe signal during the wafer burn-in test by using external input address signals, thereby decreasing the number of input pads required to receive external input strobe address signals. A plurality of pulse generating units respectively delay and logically combine a plurality of external input address signals to generate pulses. Thereafter, an internal strobe signal is generated by respectively delaying and logically operating the pulses from the pulse generating units.

摘要翻译： 用于晶片老化测试的解码电路通过使用外部输入地址信号在晶片老化测试期间内部产生选通信号，从而减少接收外部输入选通地址信号所需的输入焊盘的数量。 多个脉冲发生单元分别延迟并逻辑地组合多个外部输入地址信号以产生脉冲。 此后，通过分别延迟和逻辑地操作来自脉冲发生单元的脉冲来产生内部选通信号。

公开(公告)号：US06219292B1

公开(公告)日：2001-04-17

申请号：US09475438

申请日：1999-12-30

申请人： Ji Eun Jang

发明人： Ji Eun Jang

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： The present invention relates to a semiconductor memory device which can perform an auto-refresh operation. The semiconductor memory device includes: a mode register set for programming the number of the refresh operations to be consecutively performed; a burst counter for counting the number of the refresh operations according to the output signal from the mode register set; a first timing signal generating unit for generating an internal refresh enable signal for the inside refresh operation according to the output signal from the command decoder; an internal refresh signal generating unit for outputting a previously-set number of internal refresh signals according to the output signal from the first timing signal generating unit; and a NOR gate for NORing the output signal from the command decoder and the output signal from the internal refresh signal generating unit, thereby reducing the number of commands according to a burst shape by using a burst refresh method, and decreasing power consumption during the refresh operation.

摘要翻译： 本发明涉及能够执行自动刷新操作的半导体存储器件。 半导体存储器件包括：模式寄存器组，用于对连续执行的刷新操作的编号进行编程; 突发计数器，用于根据来自模式寄存器组的输出信号对刷新操作的数量进行计数; 第一定时信号产生单元，用于根据来自命令解码器的输出信号产生用于内部刷新操作的内部刷新使能信号; 内部刷新信号生成单元，用于根据来自第一定时信号生成单元的输出信号输出预先设定数量的内部刷新信号; 以及NOR门，用于对来自命令解码器的输出信号和来自内部刷新信号产生单元的输出信号进行NORing，从而通过使用突发刷新方法来减少根据突发形状的命令数量，并且减少刷新期间的功耗 操作。

公开(公告)号：US07826304B2

公开(公告)日：2010-11-02

申请号：US12181426

申请日：2008-07-29

申请人： Ji Eun Jang

发明人： Ji Eun Jang

IPC分类号： G11C8/00

CPC分类号： G11C5/14 ,  G11C5/144 ,  G11C7/22 ,  G11C2207/2227

摘要： A power-down control circuit utilizes the control signals employed in an active mode operation to operate when a power-down mode entry command is received during an active mode operation. The circuit is simplified requiring less area for devising the control circuit while lowering power consumption. The power-down control circuit in a semiconductor memory device includes at least a clock enable buffer unit, an external clock buffer unit, a latch unit, a control circuit for controlling internally operating clocks employed in active mode operation by using a control signal used in the active mode operation when a power-down mode entry command is received during the active mode operation, and a clock enable generation circuit for outputting clock enable signals for enabling entry to the power-down mode by using the clock control signals, when the external clock pulse signal is low level.

摘要翻译： 当在活动模式操作期间接收到掉电模式进入命令时，断电控制电路利用在主动模式操作中采用的控制信号来操作。 电路简化，在降低功耗的同时，需要较少的面积来设计控制电路。 半导体存储装置中的掉电控制电路至少包括时钟使能缓冲器单元，外部时钟缓冲器单元，锁存单元，控制电路，用于通过使用控制信号控制在主动模式操作中使用的内部工作时钟 在活动模式操作期间接收掉电模式输入命令时的主动模式操作;以及时钟使能发生电路，用于通过使用时钟控制信号输出用于使得能够进入掉电模式的时钟使能信号，当外部 时钟脉冲信号为低电平。

公开(公告)号：US07420873B2

公开(公告)日：2008-09-02

申请号：US11652786

申请日：2007-01-12

申请人： Ji Eun Jang

发明人： Ji Eun Jang

IPC分类号： G11C7/22 ,  G11C8/18

CPC分类号： G11C5/14 ,  G11C5/144 ,  G11C7/22 ,  G11C2207/2227

摘要： A power-down control circuit utilizes the control signals employed in an active mode operation to operate when a power-down mode entry command is received during an active mode operation. The circuit is simplified requiring less area for devising the control circuit while lowering power consumption. The power-down control circuit in a semiconductor memory device includes at least a clock enable buffer unit, an external clock buffer unit, a latch unit, a control circuit for controlling internally operating clocks employed in active mode operation by using a control signal used in the active mode operation when a power-down mode entry command is received during the active mode operation, and a clock enable generation circuit for outputting clock enable signals for enabling entry to the power-down mode by using the clock control signals, when the external clock pulse signal is low level.

摘要翻译： 当在活动模式操作期间接收到掉电模式进入命令时，断电控制电路利用在主动模式操作中采用的控制信号来操作。 电路简化，在降低功耗的同时，需要较少的面积来设计控制电路。 半导体存储装置中的掉电控制电路至少包括时钟使能缓冲器单元，外部时钟缓冲器单元，锁存单元，控制电路，用于通过使用控制信号控制在主动模式操作中使用的内部工作时钟 在活动模式操作期间接收掉电模式输入命令时的主动模式操作;以及时钟使能发生电路，用于通过使用时钟控制信号输出用于使得能够进入掉电模式的时钟使能信号，当外部 时钟脉冲信号为低电平。

公开(公告)号：US08824227B2

公开(公告)日：2014-09-02

申请号：US13585928

申请日：2012-08-15

申请人： Bo Yeun Kim ,  Ji Eun Jang

发明人： Bo Yeun Kim ,  Ji Eun Jang

IPC分类号： G11C29/26

CPC分类号： G11C29/28 ,  G11C29/40 ,  G11C2029/2602

摘要： A parallel test circuit of a semiconductor memory apparatus includes a memory bank which includes first and second sub banks having test global lines, respectively, and sharing a global line connected to each of the first and second sub banks. When a read command is applied during a test mode, the parallel test circuit compares data loaded in the global line to data loaded in the test global line of the second sub bank to attain a comparison result, compresses the comparison result to attain a compression signal, and outputs the compression signal as a test output signal to a pad.

摘要翻译： 半导体存储器装置的并行测试电路包括分别包括具有测试全局线的第一和第二子组以及共享连接到第一和第二子组中的每一个的全局线的存储体。 当在测试模式期间应用读命令时，并行测试电路将加载在全局线中的数据与加载在第二子库的测试全局线中的数据进行比较以获得比较结果，压缩比较结果以获得压缩信号 ，并将压缩信号作为测试输出信号输出到焊盘。

公开(公告)号：US07193906B2

公开(公告)日：2007-03-20

申请号：US11008672

申请日：2004-12-10

申请人： Ji Eun Jang ,  Kee Teok Park

发明人： Ji Eun Jang ,  Kee Teok Park

IPC分类号： G11C5/14

CPC分类号： G11C29/021 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4094 ,  G11C29/028 ,  G11C2029/5004

摘要： Provided is concerned with a voltage regulation circuit and method of regulating the voltage, including a reference voltage generator for generating a reference voltage by dividing a core voltage of a semiconductor memory device, a controller for controlling the reference voltage generator to adjust the reference voltage without handling the core voltage in response to a test signal of a test mode, and a voltage generator for generating a bit-line precharging voltage and/or a cell plate voltage in accordance with the reference voltage.

摘要翻译： 关于电压调节电路和调节电压的方法，包括用于通过划分半导体存储器件的芯电压来产生参考电压的参考电压发生器，用于控制参考电压发生器的控制器，以在没有 响应于测试模式的测试信号处理核心电压;以及电压发生器，用于根据参考电压产生位线预充电电压和/或单元板电压。

公开(公告)号：US07107500B2

公开(公告)日：2006-09-12

申请号：US10629672

申请日：2003-07-30

申请人： Ji Eun Jang

发明人： Ji Eun Jang

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/46

摘要： A test mode circuit of a semiconductor memory device features a test mode controller, a test mode decoder and a test mode item selecting means. The test mode controller outputs a test mode setting signal to control a test mode setting operation in response to a register set signal and address signals which are used in setting a test mode. The test mode decoder, which is controlled by the test mode setting signal, selects a test mode item group in response to upper address bits of the address signal. The particular test mode is then selected from the test mode group in response to lower address bits of the address signal. Accordingly, the number of metal lines used in a test mode circuit can be reduced.

摘要翻译： 半导体存储器件的测试模式电路具有测试模式控制器，测试模式解码器和测试模式项目选择装置。 测试模式控制器输出测试模式设置信号，以响应于在设置测试模式中使用的寄存器设置信号和地址信号来控制测试模式设置操作。 由测试模式设置信号控制的测试模式解码器响应于地址信号的高地址位选择测试模式项目组。 响应于地址信号的较低地址位，从测试模式组中选择特定测试模式。 因此，可以减少在测试模式电路中使用的金属线的数量。