公开(公告)号：US20070276988A1

公开(公告)日：2007-11-29

申请号：US11779804

申请日：2007-07-18

申请人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  David Chow

发明人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  David Chow

IPC分类号： G06F13/28

CPC分类号： G06F12/0246 ,  G06F12/0292 ,  G06F13/28 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.

摘要翻译： 闪存控制器适于与主机和闪存进行通信，并且包括被配置为存储可通过物理地址寻址的逻辑地址的页块表的易失性存储器。 逻辑地址由控制器用于识别块。 该表具有地址映射表和属性值表，属性值表包括属性值，每当一个块写入最大值并且与预定的块相关联时，每个属性值都被增加， 指示块的写入次数的一组块，对应于地址映射表的逻辑地址的属性值，其中预定块组的属性值的最大数量可以与 最大数量的另一组块的属性值。

公开(公告)号：US20080037321A1

公开(公告)日：2008-02-14

申请号：US11774906

申请日：2007-07-09

申请人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  David Chow

发明人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  David Chow

IPC分类号： G11C16/06

CPC分类号： G11C16/102 ,  G06F8/65 ,  G11C2211/5641

摘要： A flash memory system includes a multi level cell (MLC) flash memory organized into blocks and having pages of information, which has data and spare. The MLC flash memory includes at least a temporary area to store at least a portion of a page of information during a partial write operation. The MLC flash memory stores a page of information into a block identified by a target physical address. The flash memory system further includes a flash card micro-controller causes communication between a host flash card controller and the MLC flash memory and includes a buffer memory configured to store a portion of a page of information, where the micro-controller writes the at least a portion of a page of information to the temporary area and later copies the written at least a portion of a page of information into the block identified by a target physical address.

摘要翻译： 闪存系统包括组织成块并具有数据和备用的信息页的多级单元（MLC）闪存。 在部分写入操作期间，MLC闪速存储器至少包括用于存储信息页的至少一部分的临时区域。 MLC闪速存储器将一页信息存储到由目标物理地址识别的块中。 闪存系统还包括闪存卡微控制器引起主机闪存卡控制器和MLC闪速存储器之间的通信，并且包括被配置为存储信息页的一部分的缓冲存储器，其中微控制器写入至少 信息页面的一部分到临时区域，并且稍后将写入信息页的至少一部分复制到由目标物理地址识别的块中。

公开(公告)号：US20070276987A1

公开(公告)日：2007-11-29

申请号：US11767417

申请日：2007-06-22

申请人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  David Chow

发明人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  David Chow

IPC分类号： G06F12/02

CPC分类号： G06F13/28 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A flash memory system includes flash memory organized into a plurality of blocks of pages for storage of information, a page including data and spare, the blocks being identifiable, within the flash memory, by a physical address. The system further has a flash controller for communicating with a host and the flash memory and includes volatile memory for storing a source-shadow table of logical addresses identifying blocks addressable by the physical addresses. The source-shadow table has an address mapping table and a property value table. The property value table is used to store property values, each of which is associated with a block of a predetermined group of blocks and is indicative of the number of times a block has been written since the last erase operation performed thereon. The property values correspond to the logical addresses of the address mapping table, wherein a block having been written no more than two times is re-written to different areas of the flash memory without requiring an erase operation.

摘要翻译： 闪速存储器系统包括组织成多个页面块的闪存，用于存储信息，包括数据和备用的页面，所述块可被闪存存储器内的物理地址识别。 该系统还具有用于与主机和闪速存储器进行通信的闪存控制器，并且包括用于存储识别通过物理地址可寻址的块的逻辑地址的源影子表的易失性存储器。 source-shadow表有一个地址映射表和一个属性值表。 属性值表用于存储属性值，每个属性值与预定块块组相关联，并且表示自上次执行的上次擦除操作以来写入块的次数。 属性值对应于地址映射表的逻辑地址，其中已经写入不超过两次的块被重写到闪速存储器的不同区域，而不需要擦除操作。

公开(公告)号：US20070233955A1

公开(公告)日：2007-10-04

申请号：US11679716

申请日：2007-02-27

申请人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  Ming-Shiang Shen

发明人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  Ming-Shiang Shen

IPC分类号： G06F13/00

CPC分类号： H01R13/629 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： A Secure Digital (SD) flash microcontroller includes a memory interface to SRAM or DRAM, a flash-memory interface, and a SD interface to an SD bus. The flash memory can be on a flash bus or on the SD bus. The microcontroller is booted from boot code stored in the flash memory. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM.

摘要翻译： 安全数字（SD）闪存微控制器包括到SRAM或DRAM的存储器接口，闪存存储器接口和到SD总线的SD接口。 闪存可以在闪存总线或SD总线上。 微控制器从存储在闪存中的引导代码引导。 初始引导加载程序由状态机从闪存的第一页读取并写入小RAM。 微控制器中的中央处理单元（CPU）从小型RAM读取指令，执行初始启动加载程序，从Flash读取更多的页面。 这些页面被小RAM缓冲并写入较大的DRAM。 一旦将扩展引导顺序写入DRAM，CPU将切换一个RAM_BASE位，以使DRAM从DRAM获取指令。 然后从DRAM执行扩展启动顺序，将OS映像从闪存复制到DRAM。

公开(公告)号：US20070168614A1

公开(公告)日：2007-07-19

申请号：US11625310

申请日：2007-01-20

申请人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  Ming-Shiang Shen

发明人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F13/385

摘要： An adaptable-capacity Secure Digital (SD) card operates as a standard-capacity SD card for a standard-capacity SD 2.0 or 1.x host, and operates as a high-capacity SD card when connected to a high-capacity SD 2.0 host. A 32-bit argument received in a SD bus transaction from the host may be a 32-bit address, which can access 4 G bytes of flash memory in standard-capacity mode. For high-capacity mode, the addressable unit is a 512-byte sector, greatly increasing the addressable memory size. A SD protocol interface on a controller chip performs handshaking with the host to determine the SD version and memory capacity of the host. Host addresses are sent as byte or sector addresses to a flash memory manager on the controller chip, depending on the capacity mode agreed on during the handshaking. Memory areas on the adaptable-capacity SD card for high and standard modes can be separate or overlapping.

摘要翻译： 适用于容量的安全数字（SD）卡作为标准容量SD 2.0或1.x主机的标准容量SD卡运行，并连接到大容量SD 2.0主机时作为高容量SD卡运行 。 来自主机的SD总线事务中接收到的32位参数可以是32位地址，可以在标准容量模式下访问4 G字节的闪存。 对于高容量模式，可寻址单元是一个512字节的扇区，大大增加了可寻址的存储器大小。 控制器芯片上的SD协议接口与主机执行握手，以确定主机的SD版本和内存容量。 主机地址作为字节或扇区地址发送到控制器芯片上的闪存管理器，这取决于握手期间商定的容量模式。 适用于高容量SD卡的存储区域可以分开或重叠。

公开(公告)号：US20070147157A1

公开(公告)日：2007-06-28

申请号：US11625309

申请日：2007-01-20

申请人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  Ming-Shiang Shen

发明人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  Ming-Shiang Shen

IPC分类号： G11C5/14

CPC分类号： G11C5/143 ,  G11C5/147 ,  G11C16/30

摘要： A dual-voltage secure digital (SD) card can be inserted into a legacy host or a newer host. Legacy hosts drive a high voltage such as 3.3 volts onto the power line of the SD bus, while newer hosts drive the power line with a reduced voltage such as 1.8 volts. A flash and voltage controller chip on the SD card has a controller core that operates at the reduced voltage. A voltage regulator on the SD card, or a power management unit inside the controller chip generates an internal power voltage of 1.8 volts from the dual-voltage SD bus power line. The internal power voltage is applied to the controller core and to a voltage converter that generates a flash power voltage from the internal power voltage. The flash power voltage is applied to flash-memory chips on the SD card that operate at the higher voltage.

摘要翻译： 可以将双电压安全数字（SD）卡插入到旧式主机或更新的主机中。 传统主机将高压（例如3.3伏特）驱动到SD总线的电源线上，而较新的主机则以1.8伏特的降低电压驱动电源线。 SD卡上的闪存和电压控制器芯片具有以降低的电压工作的控制器核心。 SD卡上的电压调节器或控制器芯片内的电源管理单元从双电压SD总线电源线产生1.8伏特的内部电源电压。 内部电源电压被施加到控制器核心和电压转换器，其从内部电源电压产生闪光电源电压。 闪存电源电压被施加到在更高电压下工作的SD卡上的闪存芯片。

公开(公告)号：US07818492B2

公开(公告)日：2010-10-19

申请号：US11767417

申请日：2007-06-22

申请人： Jianjun Luo ,  Chris Tsu ,  Charles Chung Lee ,  David Queichang Chow

发明人： Jianjun Luo ,  Chris Tsu ,  Charles Chung Lee ,  David Queichang Chow

IPC分类号： G06F13/00

CPC分类号： G06F13/28 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A flash memory system includes flash memory organized into a plurality of blocks of pages for storage of information, a page including data and spare, the blocks being identifiable, within the flash memory, by a physical address. The system further has a flash controller for communicating with a host and the flash memory and includes volatile memory for storing a source-shadow table of logical addresses identifying blocks addressable by the physical addresses. The source-shadow table has an address mapping table and a property value table. The property value table is used to store property values, each of which is associated with a block of a predetermined group of blocks and is indicative of the number of times a block has been written since the last erase operation performed thereon. The property values correspond to the logical addresses of the address mapping table, wherein a block having been written no more than two times is re-written to different areas of the flash memory without requiring an erase operation.

摘要翻译： 闪速存储器系统包括组织成多个页面块的闪存，用于存储信息，包括数据和备用的页面，所述块可被闪存存储器内的物理地址识别。 该系统还具有用于与主机和闪速存储器进行通信的闪存控制器，并且包括用于存储识别通过物理地址可寻址的块的逻辑地址的源影子表的易失性存储器。 source-shadow表有一个地址映射表和一个属性值表。 属性值表用于存储属性值，每个属性值与预定块块组相关联，并且表示自上次执行的上次擦除操作以来写入块的次数。 属性值对应于地址映射表的逻辑地址，其中已经写入不超过两次的块被重写到闪速存储器的不同区域，而不需要擦除操作。

公开(公告)号：US07769944B2

公开(公告)日：2010-08-03

申请号：US11774906

申请日：2007-07-09

申请人： Jianjun Luo ,  Chris Tsu ,  Charles Chung Lee ,  David Queichang Chow

发明人： Jianjun Luo ,  Chris Tsu ,  Charles Chung Lee ,  David Queichang Chow

IPC分类号： G06F12/00

CPC分类号： G11C16/102 ,  G06F8/65 ,  G11C2211/5641

摘要： A flash memory system includes a multi level cell (MLC) flash memory organized into blocks and having pages of information, which has data and spare. The MLC flash memory includes at least a temporary area to store at least a portion of a page of information during a partial write operation. The MLC flash memory stores a page of information into a block identified by a target physical address. The flash memory system further includes a flash card micro-controller causes communication between a host flash card controller and the MLC flash memory and includes a buffer memory configured to store a portion of a page of information, where the micro-controller writes the at least a portion of a page of information to the temporary area and later copies the written at least a portion of a page of information into the block identified by a target physical address.

摘要翻译： 闪存系统包括组织成块并具有数据和备用的信息页的多级单元（MLC）闪存。 在部分写入操作期间，MLC闪速存储器至少包括用于存储信息页的至少一部分的临时区域。 MLC闪速存储器将一页信息存储到由目标物理地址识别的块中。 闪存系统还包括闪存卡微控制器引起主机闪存卡控制器和MLC闪速存储器之间的通信，并且包括被配置为存储信息页的一部分的缓冲存储器，其中微控制器写入至少 信息页面的一部分到临时区域，并且稍后将写入信息页的至少一部分复制到由目标物理地址识别的块中。

公开(公告)号：US07680977B2

公开(公告)日：2010-03-16

申请号：US11779804

申请日：2007-07-18

申请人： Jianjun Luo ,  Chris Tsu ,  Charles Chung Lee ,  David Queichang Chow

发明人： Jianjun Luo ,  Chris Tsu ,  Charles Chung Lee ,  David Queichang Chow

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0292 ,  G06F13/28 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.

摘要翻译： 闪存控制器适于与主机和闪存进行通信，并且包括被配置为存储可通过物理地址寻址的逻辑地址的页块表的易失性存储器。 逻辑地址由控制器用于识别块。 该表具有地址映射表和属性值表，属性值表包括属性值，每当一个块写入最大值并且与预定的块相关联时，每个属性值都被增加， 指示块的写入次数的一组块，对应于地址映射表的逻辑地址的属性值，其中预定块组的属性值的最大数量可以与 最大数量的另一组块的属性值。

公开(公告)号：US20100146256A1

公开(公告)日：2010-06-10

申请号：US12651321

申请日：2009-12-31

申请人： Jianjun Luo ,  Chris Tsu ,  Charles C. Lee ,  Ming-Shiang Shen

发明人： Jianjun Luo ,  Chris Tsu ,  Charles C. Lee ,  Ming-Shiang Shen

IPC分类号： G06F15/177 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F12/1416 ,  G06F12/0638 ,  G06F21/575 ,  G06F21/85 ,  G06F2221/2105 ,  G06K19/07 ,  G06K19/07354

摘要： A Secure Digital (SD) flash microcontroller includes a memory interface to SRAM or DRAM, a flash-memory interface, and a SD interface to an SD bus. The flash memory can be on a flash bus or on the SD bus. The microcontroller is booted from boot code stored in the flash memory. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM.

摘要翻译： 安全数字（SD）闪存微控制器包括到SRAM或DRAM的存储器接口，闪存存储器接口和到SD总线的SD接口。 闪存可以在闪存总线或SD总线上。 微控制器从存储在闪存中的引导代码引导。 初始引导加载程序由状态机从闪存的第一页读取并写入小RAM。 微控制器中的中央处理单元（CPU）从小型RAM读取指令，执行初始启动加载程序，从Flash读取更多的页面。 这些页面被小RAM缓冲并写入较大的DRAM。 一旦将扩展引导顺序写入DRAM，CPU将切换一个RAM_BASE位，以使DRAM从DRAM获取指令。 然后从DRAM执行扩展启动顺序，将OS映像从闪存复制到DRAM。