公开(公告)号：US20060095878A1

公开(公告)日：2006-05-04

申请号：US11005647

申请日：2004-12-06

申请人： Jiann-Tsuen Chen ,  Jean-Huang Chen

发明人： Jiann-Tsuen Chen ,  Jean-Huang Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： In a video system, a method and system for design verification of video processing systems with unbalanced data flow are provided. Efficient design verification may be provided for multi-field video processors with separate control data flow and video data flow. A design verification architecture may utilize a reference model to generate test and expected data for a controller and/or a data processor in a multi-field video processor hardware model. The design verification architecture may provide test data via stimulus feeders and may compare simulated and expected data in result checkers. When the controller is selected for verification, the design verification architecture may verify the operation and design of the multi-field video processor control data flow implementation. When the data processor is selected for verification, the design verification architecture may verify the operation and design of the multi-field video processor video data flow implementation.

公开(公告)号：US20060069542A1

公开(公告)日：2006-03-30

申请号：US11005092

申请日：2004-12-06

申请人： Jiann-Tsuen Chen ,  Jean-Huang Chen

发明人： Jiann-Tsuen Chen ,  Jean-Huang Chen

IPC分类号： G06F9/45

CPC分类号： H04N7/012 ,  G09G2310/0229 ,  G09G2320/0261 ,  H04N7/0112

摘要： In a video system, a method and system for efficient design verification of a motion adaptive deinterlacer (MAD) are provided. A MAD reference model may be configured via a configuration file to generate test parameters for the verification of a MAD hardware model. Test-bench interface drivers and a verification monitor may be utilized to transfer test parameters to the MAD hardware model and to verify simulated results. Modes of verification may comprise a normal mode, a pixel processing mode, and a field controller mode. During the normal mode, simulated pixel information and register settings generated by the pixel processor and field controller in the MAD hardware model may be compared to expected pixel information and register settings generated by the MAD reference model. During the pixel processing mode, expected and simulated pixel information may be compared. During the field controller mode, expected and simulated register settings may be compared.

公开(公告)号：US07630870B2

公开(公告)日：2009-12-08

申请号：US11005092

申请日：2004-12-06

申请人： Jiann-Tsuen Chen ,  Jean-Huang Chen

发明人： Jiann-Tsuen Chen ,  Jean-Huang Chen

IPC分类号： G06F7/48

CPC分类号： H04N7/012 ,  G09G2310/0229 ,  G09G2320/0261 ,  H04N7/0112

摘要： In a video system, a method and system for efficient design verification of a motion adaptive deinterlacer (MAD) are provided. A MAD reference model may be configured via a configuration file to generate test parameters for the verification of a MAD hardware model. Test-bench interface drivers and a verification monitor may be utilized to transfer test parameters to the MAD hardware model and to verify simulated results. Modes of verification may comprise a normal mode, a pixel processing mode, and a field controller mode. During the normal mode, simulated pixel information and register settings generated by the pixel processor and field controller in the MAD hardware model may be compared to expected pixel information and register settings generated by the MAD reference model. During the pixel processing mode, expected and simulated pixel information may be compared. During the field controller mode, expected and simulated register settings may be compared.

摘要翻译： 在视频系统中，提供了一种用于运动自适应解交错器（MAD）的有效设计验证的方法和系统。 可以通过配置文件配置MAD参考模型，以生成用于验证MAD硬件模型的测试参数。 可以使用测试台接口驱动程序和验证监视器将测试参数传输到MAD硬件模型并验证模拟结果。 验证模式可以包括正常模式，像素处理模式和现场控制器模式。 在正常模式下，可以将由MAD硬件模型中的像素处理器和现场控制器生成的模拟像素信息和寄存器设置与MAD参考模型生成的预期像素信息和寄存器设置进行比较。 在像素处理模式期间，可以比较期望的和模拟的像素信息。 在现场控制器模式期间，可以比较预期和模拟寄存器设置。

公开(公告)号：US07558718B2

公开(公告)日：2009-07-07

申请号：US11005647

申请日：2004-12-06

申请人： Jiann-Tsuen Chen ,  Jean-Huang Chen

发明人： Jiann-Tsuen Chen ,  Jean-Huang Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： In a video system, a method and system for design verification of video processing systems with unbalanced data flow are provided. Efficient design verification may be provided for multi-field video processors with separate control data flow and video data flow. A design verification architecture may utilize a reference model to generate test and expected data for a controller and/or a data processor in a multi-field video processor hardware model. The design verification architecture may provide test data via stimulus feeders and may compare simulated and expected data in result checkers. When the controller is selected for verification, the design verification architecture may verify the operation and design of the multi-field video processor control data flow implementation. When the data processor is selected for verification, the design verification architecture may verify the operation and design of the multi-field video processor video data flow implementation.

摘要翻译： 在视频系统中，提供了具有不平衡数据流的视频处理系统的设计验证方法和系统。 可以为具有单独的控制数据流和视频数据流的多场视频处理器提供有效的设计验证。 设计验证架构可以利用参考模型来在多场视频处理器硬件模型中为控制器和/或数据处理器生成测试和预期数据。 设计验证架构可以通过激励馈线提供测试数据，并可以比较结果检查器中的模拟和预期数据。 当选择控制器进行验证时，设计验证架构可以验证多场视频处理器控制数据流实现的操作和设计。 当选择数据处理器进行验证时，设计验证架构可以验证多场视频处理器视频数据流实现的操作和设计。

公开(公告)号：US20050270300A1

公开(公告)日：2005-12-08

申请号：US11016999

申请日：2004-12-20

申请人： Genkun Yang ,  Jean-Huang Chen ,  Richard Wyman

发明人： Genkun Yang ,  Jean-Huang Chen ,  Richard Wyman

IPC分类号： G09G5/36

CPC分类号： H04N1/32358 ,  G11C19/00 ,  H04N2201/3294

摘要： Various aspects of the low cost line buffer system allow a reduction in circuitry versus conventional approaches to line buffer design. A plurality of line buffers such that the output of one line buffer in the plurality of line buffers may be coupled to an input of a succeeding line buffer in the plurality of line buffers. A first line buffer in the plurality of line buffers may be coupled to an input write data signal, while the width of a subsequent plurality of line buffers may be less than or equal to the width of the previous line buffers in the plurality of line buffers.

摘要翻译： 低成本线路缓冲器系统的各个方面允许减少电路与传统的线路缓冲器设计方法。 多个行缓冲器，使得多个行缓冲器中的一行缓冲器的输出可以耦合到多个行缓冲器中的后续行缓冲器的输入。 多个行缓冲器中的第一行缓冲器可以耦合到输入写入数据信号，而后续多个行缓冲器的宽度可以小于或等于多个行缓冲器中的前一行缓冲器的宽度 。

公开(公告)号：US07453761B2

公开(公告)日：2008-11-18

申请号：US11016999

申请日：2004-12-20

申请人： Genkun Jason Yang ,  Jean-Huang Chen ,  Richard H. Wyman

发明人： Genkun Jason Yang ,  Jean-Huang Chen ,  Richard H. Wyman

IPC分类号： G06F13/14

CPC分类号： H04N1/32358 ,  G11C19/00 ,  H04N2201/3294

摘要： Various aspects of the low cost line buffer system allow a reduction in circuitry versus conventional approaches to line buffer design. A plurality of line buffers such that the output of one line buffer in the plurality of line buffers may be coupled to an input of a succeeding line buffer in the plurality of line buffers. A first line buffer in the plurality of line buffers may be coupled to an input write data signal, while the width of a subsequent plurality of line buffers may be less than or equal to the width of the previous line buffers in the plurality of line buffers.

摘要翻译： 低成本线路缓冲器系统的各个方面允许减少电路与传统的线路缓冲器设计方法。 多个行缓冲器，使得多个行缓冲器中的一行缓冲器的输出可以耦合到多个行缓冲器中的后续行缓冲器的输入。 多个行缓冲器中的第一行缓冲器可以耦合到输入写入数据信号，而后续多个行缓冲器的宽度可以小于或等于多个行缓冲器中的前一行缓冲器的宽度 。