Deep well implant structure providing latch-up resistant CMOS semiconductor product
    1.
    发明授权
    Deep well implant structure providing latch-up resistant CMOS semiconductor product 有权
    深阱注入结构提供可锁定CMOS半导体产品

    公开(公告)号:US06992361B2

    公开(公告)日:2006-01-31

    申请号:US10761658

    申请日:2004-01-20

    IPC分类号: H01L29/00

    摘要: A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.

    摘要翻译: CMOS半导体产品使用第一极性的第一掺杂阱和与第一极性相反的第二极性的第二掺杂阱,每个在半导体衬底内横向分离形成。 第一掺杂阱进一步嵌入在第二极性的第三掺杂阱中,其进一步将第一掺杂阱与第二掺杂阱分离。 第三掺杂阱为形成在第一掺杂阱和第二掺杂阱内的一对MOS晶体管提供闩锁电阻。

    Deep well implant structure providing latch-up resistant CMOS semiconductor product
    2.
    发明申请
    Deep well implant structure providing latch-up resistant CMOS semiconductor product 有权
    深阱注入结构提供可锁定CMOS半导体产品

    公开(公告)号:US20050158938A1

    公开(公告)日:2005-07-21

    申请号:US10761658

    申请日:2004-01-20

    IPC分类号: H01L21/8238 H01L27/092

    摘要: A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.

    摘要翻译: CMOS半导体产品使用第一极性的第一掺杂阱和与第一极性相反的第二极性的第二掺杂阱,每个在半导体衬底内横向分离形成。 第一掺杂阱进一步嵌入在第二极性的第三掺杂阱中,其进一步将第一掺杂阱与第二掺杂阱分离。 第三掺杂阱为形成在第一掺杂阱和第二掺杂阱内的一对MOS晶体管提供闩锁电阻。