公开(公告)号：US06992361B2

公开(公告)日：2006-01-31

申请号：US10761658

申请日：2004-01-20

申请人： Jiaw-Ren Shin ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Jiaw-Ren Shin ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H01L29/00

CPC分类号： H01L27/0921 ,  H01L21/823892 ,  H01L27/0928

摘要： A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.

摘要翻译： CMOS半导体产品使用第一极性的第一掺杂阱和与第一极性相反的第二极性的第二掺杂阱，每个在半导体衬底内横向分离形成。 第一掺杂阱进一步嵌入在第二极性的第三掺杂阱中，其进一步将第一掺杂阱与第二掺杂阱分离。 第三掺杂阱为形成在第一掺杂阱和第二掺杂阱内的一对MOS晶体管提供闩锁电阻。

公开(公告)号：US20050158938A1

公开(公告)日：2005-07-21

申请号：US10761658

申请日：2004-01-20

申请人： Jiaw-Ren Shin ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Jiaw-Ren Shin ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/0921 ,  H01L21/823892 ,  H01L27/0928

摘要： A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.

摘要翻译： CMOS半导体产品使用第一极性的第一掺杂阱和与第一极性相反的第二极性的第二掺杂阱，每个在半导体衬底内横向分离形成。 第一掺杂阱进一步嵌入在第二极性的第三掺杂阱中，其进一步将第一掺杂阱与第二掺杂阱分离。 第三掺杂阱为形成在第一掺杂阱和第二掺杂阱内的一对MOS晶体管提供闩锁电阻。

公开(公告)号：US20050275987A1

公开(公告)日：2005-12-15

申请号：US10867112

申请日：2004-06-14

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H01L27/02 ,  H02H3/20 ,  H03K17/0814

CPC分类号： H03K17/08142 ,  H01L27/0266

摘要： An electrostatic discharge (ESD) protection circuit and method thereof are presented. In some embodiments, a high voltage tolerant input/output circuit comprises an ESD detection circuit, a first first-type transistor, a first second-type transistor, and a second second-type transistor. The first first-type transistor and the first second-type transistor are coupled to a pad. The ESD detection circuit determines whether ESD occurs at the pad and, if so, couples the gates of the first and second second-type transistors to the second power rail.

摘要翻译： 提出了一种静电放电（ESD）保护电路及其方法。 在一些实施例中，高耐压输入/输出电路包括ESD检测电路，第一第一型晶体管，第一第二型晶体管和第二第二型晶体管。 第一第一型晶体管和第一第二型晶体管耦合到焊盘。 ESD检测电路确定ESD是否发生在焊盘处，如果是，则将第一和第二第二型晶体管的栅极耦合到第二电源轨。

公开(公告)号：US20050274990A1

公开(公告)日：2005-12-15

申请号：US10820320

申请日：2004-06-08

申请人： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H01L23/62 ,  H01L27/02 ,  H01L29/74 ,  H01L29/768 ,  H03K5/08

CPC分类号： H01L27/0292 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

公开(公告)号：US20050176195A1

公开(公告)日：2005-08-11

申请号：US11072014

申请日：2005-03-04

申请人： Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H01G4/228 ,  H01G4/35 ,  H01L21/8234 ,  H01L23/60 ,  H02H9/00

CPC分类号： H01L27/0251

摘要： A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.

公开(公告)号：US06730968B1

公开(公告)日：2004-05-04

申请号：US10205520

申请日：2002-07-25

申请人： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H01L2362

CPC分类号： H01L27/0292 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention provides two circuit embodiments for a whole chip electrostatic discharge, ESD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

摘要翻译： 本发明提供了用于整个芯片静电放电，ESD保护方案的两个电路实施例。 它还包括一种全芯片ESD保护方法。 本发明涉及将本发明的电路分配给每个输入/输出焊盘，以便提供并联的ESD电流放电路径。 本发明的优点是能够快速地形成对地的平行放电路径，以便有效地放电损坏的ESD电流，以避免电路损坏。 两个电路实施例示出了本发明的保护电路如何在未分离的I / O焊盘和已加热的I / O焊盘两端均以并联电路连接，以快速放电ESD电流。 这些保护实施例需要少量的半导体区域，因为较小的保护电路分布并放置在每个I / O焊盘的位置。

公开(公告)号：US06614078B2

公开(公告)日：2003-09-02

申请号：US10147272

申请日：2002-05-16

申请人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Ping-Lung Liao

发明人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Ping-Lung Liao

IPC分类号： H01L2976

CPC分类号： H01L21/823878 ,  H01L27/0921

摘要： CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively. In either of the two preferred embodiments the reduced shunt resistances prevent the forward biasing of the parasitic bipolar transistors of the SCR, thus insuring that the holding voltage is larger than the supply voltage.

公开(公告)号：US06420221B1

公开(公告)日：2002-07-16

申请号：US09507646

申请日：2000-02-22

申请人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-hung Chen ,  Ping-Lung Liao

发明人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-hung Chen ,  Ping-Lung Liao

IPC分类号： H01L218238

CPC分类号： H01L21/823878 ,  H01L27/0921

摘要： CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively. In either of the two preferred embodiments the reduced shunt resistances prevent the forward biasing of the parasitic bipolar transistors of the SCR, thus insuring that the holding voltage is larger than the supply voltage.

摘要翻译： 通过将p +和n +扩散保护环分别插入到半导体衬底的NMOS和PMOS源极侧中，分别描述了通过插入 - 免疫的CMOS I / O结构。 P +扩散保护环围绕各个n沟道晶体管，n +扩散保护环围绕着单独的p沟道晶体管。 连接到电源的这些保护环通过p型衬底到p +保护环或n阱到n +保护环，降低了与CMOS结构通常相关的寄生SCR的分流电阻。 在第二优选实施例中，将深p +注入植入到p +保护环或p阱拾取器中以降低寄生SCR的分流电阻。 与第一优选实施例的保护环相同的n +和p +保护环分别连接到正和负电压源。 在两个优选实施例中的任一个中，减小的分流电阻防止SCR的寄生双极晶体管的正向偏置，从而确保保持电压大于电源电压。

公开(公告)号：US08018000B2

公开(公告)日：2011-09-13

申请号：US12046216

申请日：2008-03-11

申请人： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yung-Tien Tsai ,  Anthony Oates

发明人： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yung-Tien Tsai ,  Anthony Oates

IPC分类号： H01L23/62

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/42368

摘要： Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be a higher-doped region within which the drain/source lies. The junction between the higher doping of this island region and the surrounding substrates operates to limit the amount of current that passes through the drain/source. Additionally, oxide features may be used to create an island surrounding the drain/source contact. Again, this isolating effect makes the amount of current passing through the device more uniform, which protects the device from damage due to an ESD event.

摘要翻译： 公开了高压半导体器件中的静电放电（ESD）保护，其通过产生围绕漏极或源极的隔离岛来提供晶体管漏极或源极之间的增强的电流隔离。 该隔离岛可以是漏极/源极所在的较高掺杂区域。 该岛区域和周围基板的较高掺杂之间的结点用于限制通过漏极/源极的电流量。 另外，可以使用氧化物特征来形成围绕漏极/源极接触的岛。 再次，这种隔离效应使得穿过器件的电流量更均匀，这保护了器件免受ESD事件的损害。

公开(公告)号：US20090179270A1

公开(公告)日：2009-07-16

申请号：US12046216

申请日：2008-03-11

申请人： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yung-Tien Tsai ,  Anthony Oates

发明人： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yung-Tien Tsai ,  Anthony Oates

IPC分类号： H01L23/62 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/42368

摘要： Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be a higher-doped region within which the drain/source lies. The junction between the higher doping of this island region and the surrounding substrates operates to limit the amount of current that passes through the drain/source. Additionally, oxide features may be used to create an island surrounding the drain/source contact. Again, this isolating effect makes the amount of current passing through the device more uniform, which protects the device from damage due to an ESD event.

摘要翻译： 公开了高压半导体器件中的静电放电（ESD）保护，其通过产生围绕漏极或源极的隔离岛来提供晶体管漏极或源极之间的增强的电流隔离。 该隔离岛可以是漏极/源极所在的较高掺杂区域。 该岛区域和周围基板的较高掺杂之间的结点用于限制通过漏极/源极的电流量。 另外，可以使用氧化物特征来形成围绕漏极/源极接触的岛。 再次，这种隔离效应使得穿过器件的电流量更均匀，这保护了器件免受ESD事件的损害。