公开(公告)号：US07916720B2

公开(公告)日：2011-03-29

申请号：US11861360

申请日：2007-09-26

Applicant: Jin-Ho Han ,  Han-Jin Cho

Inventor： Jin-Ho Han ,  Han-Jin Cho

IPC: H04L12/28

CPC classification number: G06F15/16

Abstract: There is provided a slave network interface circuit for improving the parallelism of an On-Chip network, including: a MUX for selecting one of a Write Address inputted from the On-Chip network and a Read Address to read data from a slave module, which is inputted from a slave network interface (SNI) controller, in response to the control of the SNI controller and inputs the selected address to the slave module; and the SNI controller for controlling writing and reading data at the slave module and generating a Read Address to store data read from the slave module and to transfer to the On-Chip network.

Abstract translation: 提供了一种用于提高片上网络的并行性的从属网络接口电路，包括：用于选择从片上网络输入的写地址中的一个的MUX和从从模块读取数据的读地址， 响应于SNI控制器的控制并将选择的地址输入到从模块，从从网络接口（SNI）控制器输入; 以及用于控制在从模块处的写入和读取数据的SNI控制器，并产生读地址以存储从从模块读取的数据并传送到片上网络。