Slave network interface circuit for improving parallelism of on-chip network and system thereof
    1.
    发明授权
    Slave network interface circuit for improving parallelism of on-chip network and system thereof 有权
    从网络接口电路,用于提高片上网络的并行性及其系统

    公开(公告)号:US07916720B2

    公开(公告)日:2011-03-29

    申请号:US11861360

    申请日:2007-09-26

    CPC classification number: G06F15/16

    Abstract: There is provided a slave network interface circuit for improving the parallelism of an On-Chip network, including: a MUX for selecting one of a Write Address inputted from the On-Chip network and a Read Address to read data from a slave module, which is inputted from a slave network interface (SNI) controller, in response to the control of the SNI controller and inputs the selected address to the slave module; and the SNI controller for controlling writing and reading data at the slave module and generating a Read Address to store data read from the slave module and to transfer to the On-Chip network.

    Abstract translation: 提供了一种用于提高片上网络的并行性的从属网络接口电路,包括:用于选择从片上网络输入的写地址中的一个的MUX和从从模块读取数据的读地址, 响应于SNI控制器的控制并将选择的地址输入到从模块,从从网络接口(SNI)控制器输入; 以及用于控制在从模块处的写入和读取数据的SNI控制器,并产生读地址以存储从从模块读取的数据并传送到片上网络。

    Multiplierless finite impulse response filter
    2.
    发明授权
    Multiplierless finite impulse response filter 有权
    无有限脉冲响应滤波器

    公开(公告)号:US06850579B2

    公开(公告)日:2005-02-01

    申请号:US09753258

    申请日:2000-12-29

    CPC classification number: H03H17/0607 H03H17/0226 H03H17/0621 H03H17/0657

    Abstract: A finite impulse response filter of 1:4 interpolation with 108 taps for outputting filter output data of 8 bits with respect to filter input data of 4 bits includes four shifting and storing unit of 27 bits for unifying bits of filter input data of 4 bits, which is 2's complement to shift and store the bi-unified input data, first selection unit for selecting any one of the input data stored in the four shifting and storing unit of 27 bits, address generating unit for generating addresses of lookup tables corresponding to each of a plurality of filter coefficients groups, first to fourth lookup table groups for generating filter outputs of each filter coefficients group, four accumulating unit for shifting the filter outputs of the filter coefficients groups respectively outputted in parallel from the first to the fourth lookup table groups, and second selection unit for serially converting the outputs from each of the four accumulators in accordance with filter coefficients groups.

    Abstract translation: 对于4位的滤波器输入数据,输出8位的8位滤波器输出数据,具有108抽头的1:4内插有限脉冲响应滤波器包括4位的4位移位和存储单元,用于4位滤波器输入数据的位的统一, 其是用于移位和存储双统一输入数据的补码,用于选择存储在27位的四个移位和存储单元中的任何一个输入数据的第一选择单元,用于生成与每个对应的查找表的地址的地址生成单元 多个滤波器系数组的第一至第四查找表组,用于产生每个滤波器系数组的滤波器输出;四个累加单元,用于将由第一至第四查找表组并行输出的滤波器系数组的滤波器输出移位; 以及第二选择单元,用于根据滤波器系数组串行转换四个累加器中的每一个的输出。

    Turbo decoder using binary LogMAP algorithm and method of implementing the same
    3.
    发明授权
    Turbo decoder using binary LogMAP algorithm and method of implementing the same 有权
    Turbo解码器采用二进制LogMAP算法和实现方法相同

    公开(公告)号:US06772389B2

    公开(公告)日:2004-08-03

    申请号:US09966201

    申请日:2001-09-26

    Abstract: Disclosed are a turbo decoder, which applies a base-2 binary LogMAP algorithm in implementing a turbo decoder to thereby reduce the hardware requirement and implement a high-speed turbo decoder, which comprising a split for splitting the sum of two input state metrics into an integral and a decimal part; a comparator for comparing the integral parts of the two state metrics to extract a maximum and a minimum integer; a subtractor for obtaining a difference between the original integral part and the maximum or minimum integer value; a lookup table for calculating the sum of exponential terms of base-2 function in the decimal parts; a shifter for shifting only a decimal part with a smaller integral part by the difference; an adder for adding the decimal part and a decimal part with a larger integral part; a log pre-processing block for applying a base-2 logarithm on the decimal part to thereby obtain a final value for the decimal part; and an adder for adding the maximum integral value and the final value for the decimal part to thereby obtain a final value of the base-2 function.

    Abstract translation: 公开了一种turbo解码器,其在实现turbo解码器中应用基2二进制LogMAP算法,从而降低硬件要求并实现高速turbo解码器,该高速turbo解码器包括用于将两个输入状态度量的和分解为 积分和小数部分; 用于比较两个状态度量的积分部分以提取最大和最小整数的比较器; 用于获得原始积分部分与最大或最小整数值之间的差的减法器; 用于计算小数部分中base-2函数的指数项的和的查找表; 移位器,用于仅移动具有较小整数部分的小数部分的差值; 用于将小数部分和小数部分与较大整数部分相加的加法器; 用于在小数部分应用基2对数的日志预处理块,从而获得小数部分的最终值; 以及加法器,用于将最大积分值和小数部分的最终值相加,从而获得基2功能的最终值。

    OCN-based moving picture decoder
    4.
    发明授权
    OCN-based moving picture decoder 有权
    基于OCN的运动图像解码器

    公开(公告)号:US08526503B2

    公开(公告)日:2013-09-03

    申请号:US11933060

    申请日:2007-10-31

    CPC classification number: H04N19/436 H04N19/42 H04N19/423 H04N19/44

    Abstract: A moving picture decoder further includes a plurality of switches in a mesh configuration, and at least one On-Chip Network (OCN) arranged in a star configuration and coupled to the plurality of switches. The On-Chip Network (OCN) includes a plurality of slave modules coupled to the On-Chip Network (OCN) and arranged in a star configuration.

    Abstract translation: 运动图像解码器还包括网格配置中的多个交换机以及以星形配置并耦合到多个交换机的至少一个片上网络(OCN)。 片上网络(OCN)包括耦合到片上网络(OCN)并以星形配置布置的多个从模块。

    SELF-CONTROLLED FUNCTIONAL MODULE, AND CONTROL METHOD THEREFOR AND SYSTEM USING THE SAME
    5.
    发明申请
    SELF-CONTROLLED FUNCTIONAL MODULE, AND CONTROL METHOD THEREFOR AND SYSTEM USING THE SAME 审中-公开
    自控功能模块及其使用的控制方法及系统

    公开(公告)号:US20090013093A1

    公开(公告)日:2009-01-08

    申请号:US12111522

    申请日:2008-04-29

    CPC classification number: G06F9/3867

    Abstract: Provided are a self-controlled functional module, and a control method therefor and a system using the same. The functional module, includes: a data input unit for receiving data; a function process unit for performing a specific function based on input data transmitted through the data input unit; a data output unit for outputting a result processed by the function process unit; and an operation control unit for receiving state information individually from the data input unit and the data output unit and controlling operation start of the function process unit based on state information of the data input unit and the data output unit.

    Abstract translation: 提供了一种自我控制的功能模块及其控制方法和使用该功能模块的系统。 功能模块包括:用于接收数据的数据输入单元; 功能处理单元,用于基于通过数据输入单元发送的输入数据执行特定功能; 数据输出单元,用于输出由功能处理单元处理的结果; 以及操作控制单元,用于基于数据输入单元和数据输出单元的状态信息,从数据输入单元和数据输出单元接收状态信息,并且控制功能处理单元的操作开始。

    Wireless data communication apparatus using the diffused infrared-ray
antenna
    7.
    发明授权
    Wireless data communication apparatus using the diffused infrared-ray antenna 失效
    使用扩散红外线天线的无线数据通信装置

    公开(公告)号:US6154300A

    公开(公告)日:2000-11-28

    申请号:US968944

    申请日:1997-11-12

    Applicant: Han-Jin Cho

    Inventor: Han-Jin Cho

    CPC classification number: H04B10/1149

    Abstract: A wireless data communication apparatus using the diffused infrared-ray antennas comprising: a plurality of terminals having their own optical communication modules for transmitting and receiving infrared-ray signals, wherein the optical communication module includes a parabolic shaped infrared-ray antenna; and a repeater which receives the infrared-ray signals transmitted from the plurality of terminals and transmits the infrared-ray signals to the plurality of terminals, wherein the repeater includes a parabolic shaped infrared-ray antenna.

    Abstract translation: 一种使用扩散红外线天线的无线数据通信装置,包括:具有各自的用于发送和接收红外线信号的光通信模块的多个终端,其中所述光通信模块包括抛物线形红外线天线; 以及中继器,其接收从所述多个终端发送的红外线信号,并将所述红外线信号发送到所述多个终端,其中所述中继器包括抛物线形红外线天线。

    OCN-BASED MOVING PICTURE DECODER
    8.
    发明申请
    OCN-BASED MOVING PICTURE DECODER 有权
    基于OCN的移动图像解码器

    公开(公告)号:US20080111820A1

    公开(公告)日:2008-05-15

    申请号:US11933060

    申请日:2007-10-31

    CPC classification number: H04N19/436 H04N19/42 H04N19/423 H04N19/44

    Abstract: Provided is an On-Chip network (OCN) based moving picture decoder. The moving picture decoder includes: a plurality of switches for providing a parallel data transmission path between a predetermined master module and the other master module, a parallel data transmission path between a predetermined master module and a predetermined slave module, and a parallel data transmission path between a predetermined slave module and the other slave module; and a plurality of On-Chip Networks (OCNs) for providing a local parallel data transmission path between predetermined slave modules and a parallel data transmission path between a slave module in a corresponding area and the switches, wherein a OCN structure of the moving picture decoder globally has a mesh structure with the switches as medium and locally has a star structure with each of the ONCs as medium.

    Abstract translation: 提供了一种基于片上网络(OCN)的运动图像解码器。 运动图像解码器包括:用于在预定主模块和另一主模块之间提供并行数据传输路径的多个开关,预定主模块和预定从模块之间的并行数据传输路径以及并行数据传输路径 在预定的从模块和另一个从模块之间; 以及多个片上网络(OCN),用于在预定的从模块之间提供本地并行数据传输路径,以及在相应区域中的从模块与开关之间的并行数据传输路径,其中运动图像解码器的OCN结构 全局具有网状结构,开关为介质,局部具有星形结构,每个ONC为介质。

    108-tap 1:4 interpolation FIR filter for digital mobile telecommunication
    9.
    发明授权
    108-tap 1:4 interpolation FIR filter for digital mobile telecommunication 有权
    用于数字移动电信的108抽头1:4插值FIR滤波器

    公开(公告)号:US06888904B2

    公开(公告)日:2005-05-03

    申请号:US09866277

    申请日:2001-05-24

    CPC classification number: H03H17/0621 H03H17/0607

    Abstract: A 108-tap 1:4 interpolation FIR filter device for digital mobile telecommunication having a single bit input that employs a look-up table minimum scheme and a pipeline structure in which the size of the entire look-up tables is significantly reduced by dividing four coefficient groups into three parts, respectively, and effectively using the symmetry of the 108-tap filter coefficient and the symmetry within the look-up table. The FIR filter includes an input shift register and selector for processing a single bit input of four channels, an address generator for producing addresses of the look-up table, look-up table group 0˜3 for producing filter outputs group by group via the look-up table and the calculator using the address as an input, a pipeline register I for delaying the filter outputs for coefficient group which are outputted in parallel, a group selector for converting the delayed outputs in serial channel by channel, and a pipeline register II for matching the time of filter output channel by channel.

    Abstract translation: 具有使用查找表最小方案的单个位输入的数字移动通信的108抽头1:4内插FIR滤波器装置和通过将四个整数查找表的大小分开来显着减少整个查找表的大小的流水线结构 系数组分别分为三部分,并有效地利用了108抽头滤波器系数的对称性和查找表中的对称性。 FIR滤波器包括用于处理四个通道的单个位输入的输入移位寄存器和选择器,用于产生查找表的地址的地址发生器,用于通过组播逐个产生滤波器输出的查找表组0〜3 查找表和使用地址作为输入的计算器,用于延迟并行输出的系数组的滤波器输出的流水线寄存器I,用于逐个逐个逐个通道转换延迟输出的组选择器和流水线寄存器 II用于匹配滤波器输出通道的时间。

    Effective motion estimation for hierarchical search
    10.
    发明授权
    Effective motion estimation for hierarchical search 有权
    分层搜索的有效运动估计

    公开(公告)号:US06850569B2

    公开(公告)日:2005-02-01

    申请号:US09846153

    申请日:2001-04-30

    CPC classification number: H04N5/145 G06T7/207 H04N19/53

    Abstract: In the present invention, a reference block data within a current image from which a motion vector will be obtained and corresponding search region data within reproduced previous image are stored in a reference block and a search region data memory, respectively. A motion vector of two pixels unit is performed using the reference block and the search region data stored in the memory, thus resulting in obtained a motion vector of two pixels unit. At this time, the reference block and the search region data are used by performing 2:1 sampling in a horizontal direction and a vertical direction, respectively and the search range is −7˜+7. The structure of the motion search is consisted of a memory for storing a reference block (8×8) of current images and a memory (24×8) for storing a search region storing reproduced previous images. The structure further includes a processing element (PE) array block for obtaining SAD (sum of absolute difference) among candidate blocks within the search region and a block for obtaining the smallest motion vector among the candidate SADs. If hardware is implemented using the two-step search algorithm among the motion estimation of the present invention, a lot of data bandwidth of the reference memory and a memory having a large size are required. The down sampling scheme and the bandwidth of the reference memory has a structure in which a slice is previously downloaded before a pipeline when it downloads from the external memory. In an actual pipeline operation, it is implemented by the bandwidth of ⅓. Also, as it has independent memories, it can operate even at low frequency without degrading the performance.

    Abstract translation: 在本发明中,分别在参考块和搜索区域数据存储器中分别存储当前图像中的将获得运动矢量的参考块数据和再现的先前图像内的相应搜索区域数据。 使用存储在存储器中的参考块和搜索区域数据来执行两个像素单元的运动矢量,从而得到两个像素单位的运动矢量。 此时,通过在水平方向和垂直方向上分别进行2:1的采样来使用参考块和搜索区域数据,并且搜索范围为-7〜+ 7。 运动搜索的结构由用于存储当前图像的参考块(8×8)的存储器和用于存储存储再现的先前图像的搜索区域的存储器(24x8)组成。 该结构还包括处理元件(PE)阵列块,用于获得搜索区域内的候选块之间的SAD(绝对差之和)和用于获得候选SAD之间的最小运动矢量的块。 如果在本发明的运动估计中使用两步搜索算法实现硬件,则需要参考存储器的大量数据带宽和大尺寸的存储器。 下采样方案和参考存储器的带宽具有这样的结构,其中当从外部存储器下载时,管线之前预先下载片。 在实际流水线操作中,以1/3的带宽实现。 此外,由于它具有独立的存储器,所以即使在低频下也可以运行,而不会降低性能。

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