公开(公告)号：US20080084749A1

公开(公告)日：2008-04-10

申请号：US11844514

申请日：2007-08-24

Applicant: Jin-wook LEE ,  Jin-Yub LEE

Inventor： Jin-wook LEE ,  Jin-Yub LEE

IPC: G11C16/00

CPC classification number: G11C16/12 ,  G11C16/0483

Abstract: Provided are a circuit and method for generating a program voltage, and a non-volatile memory device using the same. The circuit, which generates a program voltage for programming a memory cell of a semiconductor memory device, includes a program voltage controller and a voltage generating unit. The program voltage controller generates a program voltage control signal according to program/erase operations information. The voltage controller generates a program voltage in response to the program voltage control signal.

Abstract translation: 提供了用于产生编程电压的电路和方法，以及使用其的非易失性存储器件。 产生用于对半导体存储器件的存储单元进行编程的编程电压的电路包括编程电压控制器和电压产生单元。 程序电压控制器根据编程/擦除操作信息产生编程电压控制信号。 电压控制器响应于编程电压控制信号产生编程电压。

公开(公告)号：US20090154281A1

公开(公告)日：2009-06-18

申请号：US12235812

申请日：2008-09-23

Applicant: Jin-wook LEE ,  Jin-yub LEE

Inventor： Jin-wook LEE ,  Jin-yub LEE

IPC: G11C5/14

CPC classification number: G11C5/14

Abstract: A semiconductor memory device includes a cell core storing data, a plurality of peripheral circuit components, collectively driving data to/from the cell core and providing a default state at an output signal state during an initialization process upon power-up, and an initialization circuit detecting a standby mode of operation for the semiconductor memory device, and upon detecting the standby mode controlling operation of the plurality of peripheral circuit components to provide the default state as the signal state during standby mode.

Abstract translation: 半导体存储器件包括：存储数据的单元核心，多个外围电路部件，共同地向单元核心驱动数据，并且在上电时的初始化处理期间以输出信号状态提供默认状态;以及初始化电路 检测半导体存储器件的待机操作模式，并且在检测到多个外围电路组件的待机模式控制操作时提供默认状态作为待机模式期间的信号状态。

公开(公告)号：US20160358925A1

公开(公告)日：2016-12-08

申请号：US15084785

申请日：2016-03-30

Applicant: Keun-hee BAI ,  Myeong-cheol KIM ,  Kwan-heum LEE ,  Do-hyoung KIM ,  Jin-wook LEE ,  Seung-mo HA ,  Dong-Hoon KHANG

Inventor： Keun-hee BAI ,  Myeong-cheol KIM ,  Kwan-heum LEE ,  Do-hyoung KIM ,  Jin-wook LEE ,  Seung-mo HA ,  Dong-Hoon KHANG

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/308 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.

Abstract translation: 半导体器件包括衬底，衬底上的鳍状有源区域图案，包括上部区域和下部区域的鳍状主动区域图案，围绕鳍状物区域图案的器件隔离层图案，在上部区域上的栅极图案 翅片有源区域图案和在翅片有源区域图案的下部区域上的应力器，其中，器件隔离层图案的顶表面比上部区域的顶表面低，并且高于下部区域的顶表面 。

公开(公告)号：US20160133632A1

公开(公告)日：2016-05-12

申请号：US14853442

申请日：2015-09-14

Applicant: Hong-bae PARK ,  Ja-hum KU ,  Myeong-cheol KIM ,  Jin-wook LEE ,  Sung-kee HAN

Inventor： Hong-bae PARK ,  Ja-hum KU ,  Myeong-cheol KIM ,  Jin-wook LEE ,  Sung-kee HAN

IPC: H01L27/11 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

Abstract translation: 一种方法包括在衬底上提供多个有源区，以及在所述多个有源区中的两个之间的至少第一器件隔离层，其中所述多个有源区在第一方向上延伸; 提供沿第二方向延伸的栅极层，所述栅极层形成多条栅极线，所述栅极线包括相对于彼此以直线延伸的第一栅极线和第二栅极线，所述第二栅极线和第二栅极线之间具有间隔，所述第一栅极 线和第二栅极线交叉有效区域中的至少一个，提供覆盖第一器件隔离层并围绕第一和第二栅极线周围的有源区域覆盖的绝缘层; 以及在所述第一栅极线和所述第二栅极线之间的空间中提供栅极间绝缘区域。