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    Semiconductor Devices Having Source/Drain Regions with Strain-Inducing Layers and Methods of Manufacturing Such Semiconductor Devices
    4.
    发明申请
    Semiconductor Devices Having Source/Drain Regions with Strain-Inducing Layers and Methods of Manufacturing Such Semiconductor Devices 有权
    具有应变诱导层的源极/漏极区域的半导体器件以及制造这种半导体器件的方法

    公开(公告)号：US20160027875A1

    公开(公告)日：2016-01-28

    申请号：US14680458

    申请日：2015-04-07

    Applicant: Seok-hoon Kim ,  Jin-bum Kim ,  Kwan-heum Lee ,  Byeong-chan Lee ,  Cho-eun Lee ,  Su-jin Jung

    Inventor： Seok-hoon Kim ,  Jin-bum Kim ,  Kwan-heum Lee ,  Byeong-chan Lee ,  Cho-eun Lee ,  Su-jin Jung

    IPC: H01L29/10 ,  H01L29/78

    CPC classification number: H01L29/7848 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

    Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.

    Abstract translation: 半导体器件包括能够对包括在小型化电子器件中的晶体管的沟道区域施加应变的应变诱导层以及半导体器件的制造方法。 半导体器件包括具有沟道区的衬底; 一对源极/漏极区，设置在所述衬底上并沿第一方向布置在所述沟道区的两侧; 以及栅极结构，设置在所述沟道区上并且包括在与所述第一方向不同的第二方向上延伸的栅极电极图案，设置在所述沟道区域和所述栅极电极图案之间的栅极介电层以及覆盖相应侧面的栅极间隔件 栅电极图案和栅介质层的表面。 源极/漏极区域中的至少一个包括第一应变诱导层和第二应变诱导层。 第一应变诱导层设置在沟道区的侧表面和第二应变诱导层之间，并与栅介质层的至少一部分接触。

    Methods of manufacturing semiconductor devices
    5.
    发明授权
    Methods of manufacturing semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US09112054B2

    公开(公告)日：2015-08-18

    申请号：US13181907

    申请日：2011-07-13

    Applicant: Kwan-Heum Lee ,  Wook-Je Kim ,  Soon-Wook Jung ,  Sang-Bom Kang ,  Ki-Hong Kim

    Inventor： Kwan-Heum Lee ,  Wook-Je Kim ,  Soon-Wook Jung ,  Sang-Bom Kang ,  Ki-Hong Kim

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78

    CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

    Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An epitaxial layer is formed on a top surface of the substrate adjacent to the gate structure. An elevated source/drain (ESD) layer and an impurity region are formed by implanting impurities and carbon in the epitaxial layer and an upper portion of the substrate using the gate structure as an ion implantation mask. A metal silicide layer is formed on the ESD layer.

    Abstract translation: 提供半导体器件和制造半导体器件的方法。 在制造半导体器件的方法中，在衬底上形成栅极结构。 在与栅极结构相邻的衬底的顶表面上形成外延层。 通过使用栅极结构作为离子注入掩模，将外延层中的杂质和碳注入到衬底的上部，形成升高的源极/漏极（ESD）层和杂质区。 在ESD层上形成金属硅化物层。

    Method of manufacturing a semiconductor device
    7.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08877583B2

    公开(公告)日：2014-11-04

    申请号：US13728622

    申请日：2012-12-27

    Applicant: Jin-Bum Kim ,  Young-Pil Kim ,  Kwan-Heum Lee ,  Sun-Ghil Lee

    Inventor： Jin-Bum Kim ,  Young-Pil Kim ,  Kwan-Heum Lee ,  Sun-Ghil Lee

    IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/285 ,  H01L21/768 ,  H01L49/02

    CPC classification number: H01L21/285 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76889 ,  H01L27/10855 ,  H01L28/91

    Abstract: In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process.

    Abstract translation: 在形成DRAM器件的欧姆层的方法中，通过在第一温度和瞬时第二次加热下的第一次热处理将存储节点接触插塞和电容器的下部电极之间的金属硅化物层形成为欧姆层 在比第一温度高的第二温度下进行处理。 因此，金属硅化物层具有热稳定的晶体结构，并且在高温工艺中在金属硅化物层上几乎或不发生聚集。 因此，尽管随后的高温处理，欧姆层的薄层电阻也可能不增加。

    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
    8.
    发明申请
    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
    制造半导体器件的方法

    公开(公告)号：US20120015490A1

    公开(公告)日：2012-01-19

    申请号：US13183630

    申请日：2011-07-15

    Applicant: Kwan-Heum LEE ,  Soon-Wook JUNG ,  Jung-Hyun PARK ,  Wook-Je KIM ,  Jong-Sang BAN

    Inventor： Kwan-Heum LEE ,  Soon-Wook JUNG ,  Jung-Hyun PARK ,  Wook-Je KIM ,  Jong-Sang BAN

    IPC: H01L21/8238 ,  H01L21/336

    CPC classification number: H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

    Abstract: A method of manufacturing a semiconductor device includes forming a gate structure on a substrate; forming a sacrificial spacer may be formed on a sidewall of the gate substrate; implanting first impurities into portions of the substrate by a first ion implantation process using the gate structure and the sacrificial spacer as ion implantation masks to form source and drain regions; removing the sacrificial spacer; and implanting second impurities and carbon atoms into portions of the substrate by a second ion implantation process using the gate structure as an ion implantation mask to form source and drain extension regions and carbon doping regions, respectively.

    Abstract translation: 一种制造半导体器件的方法包括在衬底上形成栅极结构; 形成牺牲隔离物可以形成在栅极衬底的侧壁上; 通过使用栅极结构和牺牲隔离物作为离子注入掩模的第一离子注入工艺将第一杂质注入到衬底的部分中以形成源区和漏区; 去除牺牲隔离物; 以及通过使用所述栅极结构作为离子注入掩模的第二离子注入工艺将第二杂质和碳原子注入到所述衬底的部分中，以分别形成源极和漏极延伸区域和碳掺杂区域。

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20100001349A1

    公开(公告)日：2010-01-07

    申请号：US12495501

    申请日：2009-06-30

    Applicant: Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

    Inventor： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

    IPC: H01L27/088

    CPC classification number: H01L21/823425 ,  H01L21/823418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/66825

    Abstract: A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

    Abstract translation: 半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物 电极。 高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

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