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1.发明授权Duty cycle correction of a multi-gigahertz clock signal with crossover point control 有权具有交叉点控制的多吉赫兹时钟信号的占空比校正公开(公告)号：US07496155B1
公开(公告)日：2009-02-24
申请号：US11228655
申请日：2005-09-16
申请人： Jinghui Lu , Yiqin Chen
发明人： Jinghui Lu , Yiqin Chen
IPC分类号： H04L27/00
CPC分类号： H04L25/0292 , H04L7/033
摘要： A clock recovery circuit includes a crossover adjustment circuit operable to adjust a crossover point to adjust a corresponding duty cycle. The adjustment circuit comprises a feedback adjustment combining element which is implemented as summing elements and a crossover point control clock amplifier, an operational amplifier with a resistor in place of a low pass filter at an input of the operational amplifier and feedback driver. The summing element within the feedback adjustment combining element combines input clocks with feedback signals, the crossover point control clock amplifier includes adjustment driver, the two cross coupled PMOS along with the resistor connected between them, reshape input clocks, adjust cross over point and provide output clocks with DCD corrected. A modified Miller capacitor comprising a resistor in series with a capacitor across a drain and gate of a cascode transistor pair is utilized in an output stage to adjust corner frequencies.
摘要翻译： 时钟恢复电路包括可操作以调整交叉点以调整相应的占空比的交叉调整电路。 调节电路包括反馈调整组合元件，其被实现为求和元件和交叉点控制时钟放大器，运算放大器具有电阻器，代替在运算放大器和反馈驱动器的输入处的低通滤波器。 反馈调整组合元件中的求和元素将输入时钟与反馈信号相结合，交叉点控制时钟放大器包括调整驱动器，两个交叉耦合PMOS以及连接在它们之间的电阻，重新形成输入时钟，调整交叉点并提供输出 DCD校正时钟。 一个改进的米勒电容器包括与串联晶体管对的漏极和栅极上的电容器串联的电阻器，用于输出级以调整转角频率。
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2.发明授权公开(公告)号：US06356160B1
公开(公告)日：2002-03-12
申请号：US09347256
申请日：1999-07-02
申请人： Moises E. Robinson , Bernard L. Grung , Yiqin Chen
发明人： Moises E. Robinson , Bernard L. Grung , Yiqin Chen
IPC分类号： H03L707
摘要： A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a variable gain which is controlled by an automatic gain adjust circuit. A coarse loop of the PLL allows for fast frequency acquisition of an internal oscillator.
摘要翻译： 高速数据通信系统包括从通信数据恢复数据和时钟信号的接收机。 接收器电路具有双锁相环（PLL）电路。 PLL的精细环路包括提供差分模拟电压输出的相位检测器。 跨导电路将差分模拟电压输出转换为低电流模拟输出。 跨导电路具有由自动增益调节电路控制的可变增益。 PLL的粗略回路允许快速采集内部振荡器。
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3.发明授权公开(公告)号：US07406118B2
公开(公告)日：2008-07-29
申请号：US10661016
申请日：2003-09-11
申请人： Eric D. Groen , Charles W. Boecker , William C. Black , Scott A. Irwin , Joseph N. Kryzak , Yiqin Chen , Andrew G. Jenkins , Aaron J. Hoelscher
发明人： Eric D. Groen , Charles W. Boecker , William C. Black , Scott A. Irwin , Joseph N. Kryzak , Yiqin Chen , Andrew G. Jenkins , Aaron J. Hoelscher
IPC分类号： H04B1/38
CPC分类号： H04L25/14
摘要： A programmable logic device includes a plurality of programmable multi-gigabit transceivers, programmable logic fabric, and a control module. Each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings. The programmable logic fabric is operably coupled to the plurality of programmable multi-gigabit transceivers and is configured to process at least a portion of the data being transceived via the multi-gigabit transceivers. The control module is operably coupled to produce the plurality of transceiver settings based on a desired mode of operation for the programmable logic device.
摘要翻译： 可编程逻辑器件包括多个可编程的多吉比特收发器，可编程逻辑结构和控制模块。 根据多个收发器设置，多个可编程的多吉比特收发器中的每一个被单独编程为期望的收发操作模式。 可编程逻辑结构可操作地耦合到多个可编程的多吉比特收发器，并且被配置为处理经由多吉比特收发器收发的数据的至少一部分。 控制模块可操作地耦合以基于可编程逻辑器件的期望操作模式产生多个收发器设置。
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4.发明申请公开(公告)号：US20050058187A1
公开(公告)日：2005-03-17
申请号：US10661016
申请日：2003-09-11
申请人： Eric Groen , Charles Boecker , William Black , Scott Irwin , Joseph Kryzak , Yiqin Chen , Andrew Jenkins , Aaron Hoelscher
发明人： Eric Groen , Charles Boecker , William Black , Scott Irwin , Joseph Kryzak , Yiqin Chen , Andrew Jenkins , Aaron Hoelscher
CPC分类号： H04L25/14
摘要： A programmable logic device includes a plurality of programmable multi-gigabit transceivers, programmable logic fabric, and a control module. Each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings. The programmable logic fabric is operably coupled to the plurality of programmable multi-gigabit transceivers and is configured to process at least a portion of the data being transceived via the multi-gigabit transceivers. The control module is operably coupled to produce the plurality of transceiver settings based on a desired mode of operation for the programmable logic device.
摘要翻译： 可编程逻辑器件包括多个可编程的多吉比特收发器，可编程逻辑结构和控制模块。 根据多个收发器设置，多个可编程的多吉比特收发器中的每一个被单独编程为期望的收发操作模式。 可编程逻辑结构可操作地耦合到多个可编程的多吉比特收发器，并且被配置为处理经由多吉比特收发器收发的数据的至少一部分。 控制模块可操作地耦合以基于可编程逻辑器件的期望操作模式产生多个收发器设置。
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