Video Codec Method and System
    1.
    发明申请
    Video Codec Method and System 有权
    视频编解码方法和系统

    公开(公告)号:US20110096990A1

    公开(公告)日:2011-04-28

    申请号:US12605255

    申请日:2009-10-23

    CPC classification number: H04N19/33 H04N19/103 H04N19/136 H04N19/17

    Abstract: Techniques pertaining to scalable video codec are disclosed. According to one aspect of the present invention, a video image is analyzed and a region of interest (ROI) and a region of non-interest (non-ROI) are identified. By comparing the non-ROI image with that of a previous image, a background ignored identifier is created indicating whether the non-ROI can be ignored during encoding and decoding processes. Based on the status of the background ignored identifier, the encoder encodes the images into a basic layer (BL) and an enhanced layer (EL), and transmits the coded bit streams along with the identifier to a decoder. The decoder reconstructs the image based on the identifier and the BL and the EL bit streams.

    Abstract translation: 公开了与可伸缩视频编解码器有关的技术。 根据本发明的一个方面,分析视频图像,并且识别感兴趣区域(ROI)和非感兴趣区域(非ROI)。 通过将非ROI图像与先前图像的非ROI图像进行比较,创建背景忽略的标识符,指示在编码和解码过程期间是否可以忽略非ROI。 基于背景忽略标识符的状态,编码器将图像编码为基本层(BL)和增强层(EL),并将编码的比特流与标识符一起发送到解码器。 解码器基于标识符和BL和EL比特流重构图像。

    Duty cycle correction of a multi-gigahertz clock signal with crossover point control
    2.
    发明授权
    Duty cycle correction of a multi-gigahertz clock signal with crossover point control 有权
    具有交叉点控制的多吉赫兹时钟信号的占空比校正

    公开(公告)号:US07496155B1

    公开(公告)日:2009-02-24

    申请号:US11228655

    申请日:2005-09-16

    CPC classification number: H04L25/0292 H04L7/033

    Abstract: A clock recovery circuit includes a crossover adjustment circuit operable to adjust a crossover point to adjust a corresponding duty cycle. The adjustment circuit comprises a feedback adjustment combining element which is implemented as summing elements and a crossover point control clock amplifier, an operational amplifier with a resistor in place of a low pass filter at an input of the operational amplifier and feedback driver. The summing element within the feedback adjustment combining element combines input clocks with feedback signals, the crossover point control clock amplifier includes adjustment driver, the two cross coupled PMOS along with the resistor connected between them, reshape input clocks, adjust cross over point and provide output clocks with DCD corrected. A modified Miller capacitor comprising a resistor in series with a capacitor across a drain and gate of a cascode transistor pair is utilized in an output stage to adjust corner frequencies.

    Abstract translation: 时钟恢复电路包括可操作以调整交叉点以调整相应的占空比的交叉调整电路。 调节电路包括反馈调整组合元件,其被实现为求和元件和交叉点控制时钟放大器,运算放大器具有电阻器,代替在运算放大器和反馈驱动器的输入处的低通滤波器。 反馈调整组合元件中的求和元素将输入时钟与反馈信号相结合,交叉点控制时钟放大器包括调整驱动器,两个交叉耦合PMOS以及连接在它们之间的电阻,重新形成输入时钟,调整交叉点并提供输出 DCD校正时钟。 一个改进的米勒电容器包括与串联晶体管对的漏极和栅极上的电容器串联的电阻器,用于输出级以调整转角频率。

    Apparatus and method for determining positions of pilot sub-carries in an OFDM symbol
    3.
    发明申请
    Apparatus and method for determining positions of pilot sub-carries in an OFDM symbol 有权
    用于确定OFDM符号中的导频子载波的位置的装置和方法

    公开(公告)号:US20080298485A1

    公开(公告)日:2008-12-04

    申请号:US12023034

    申请日:2008-01-31

    Applicant: JingHui LU

    Inventor: JingHui LU

    CPC classification number: H04L27/2647 H04L5/0048 H04L5/005 H04L27/2659

    Abstract: Techniques for determining positions of pilot sub-carries in a received OFDM symbol are described. Components of pilot sub-carries from a theoretical OFDM symbol are extracted to form M theoretical pilot sequences according to M possible distributions in frequency domain of the pilot sub-carries in the theoretical OFDM symbol. Components of pilot sub-carries from the received OFDM symbol are also extracted to form K hypothetical pilot sequences according to K possible distributions in frequency domain of pilot sub-carries in the received OFDM symbol. The correlations of every two adjacent elements of the theoretical pilot sequences are calculated to get M corresponding theoretical correlation sequences, and the correlations of every two adjacent elements of the hypothetical pilot sequence are also calculated to get K corresponding hypothetical correlation sequences. Sequence correlations between the hypothetical correlation sequences and the theoretical correlation sequences are then calculated. The positions of pilot sub-carriers in the received OFDM symbol can be determined from the one that has the maximum modulus value.

    Abstract translation: 描述用于确定接收的OFDM符号中的导频子载波的位置的技术。 根据理论OFDM符号中的导频子载波的频域中的M个可能分布,提取理论OFDM符号的导频子载波的分量,形成M个理论导频序列。 根据接收到的OFDM符号中的导频子载波的频域中的K个可能分布,也提取从接收的OFDM符号导频子载波的分量,以形成K个假设导频序列。 计算理论导频序列的每两个相邻元素的相关性以得到M个对应的理论相关序列,并且还计算假设导频序列的每两个相邻元素的相关性以获得K个相应的假设相关序列。 然后计算假设相关序列与理论相关序列之间的序列相关性。 可以从具有最大模数值的导频子载波中确定接收的OFDM符号中的导频子载波的位置。

    Differential signal strength detector
    4.
    发明授权
    Differential signal strength detector 有权
    差分信号强度检测器

    公开(公告)号:US07460848B1

    公开(公告)日:2008-12-02

    申请号:US10955062

    申请日:2004-09-29

    CPC classification number: H04B17/318

    Abstract: A signal detection circuit includes a first signal multiplier operably coupled to square an input signal, a second signal multiplier operably coupled to square a reference signal, and a filter module operably coupled to produce a digital output representative of the input signal based on a squared input signal and a squared reference signal.

    Abstract translation: 信号检测电路包括可操作地耦合到平方输入信号的第一信号乘法器,可操作地耦合到平方参考信号的第二信号乘法器和可操作地耦合以产生代表输入信号的数字输出的滤波器模块,其基于平方输入 信号和平方参考信号。

    Transmitter with multiphase data combiner for parallel to serial data conversion
    5.
    发明授权
    Transmitter with multiphase data combiner for parallel to serial data conversion 有权
    具有多相数据组合器的发射机,用于并行到串行数据转换

    公开(公告)号:US06611218B1

    公开(公告)日:2003-08-26

    申请号:US10043771

    申请日:2002-01-09

    CPC classification number: H03M9/00 H03L7/06

    Abstract: Described are high-speed parallel-to-serial converters. The converters include data combiners with differential current-steering circuits that respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment includes complementary data-input transistors to expedite the data combiner's response to changes in input data.

    Abstract translation: 描述了高速并行到串行转换器。 转换器包括具有差分电流 - 转向电路的数据组合器,其通过产生表示并行数据位的差分串行版本的互补电流信号来响应并行数据位。 一个实施例包括补充数据输入晶体管,以加速数据组合器对输入数据变化的响应。

    Video codec method and system
    8.
    发明授权
    Video codec method and system 有权
    视频编解码方法和系统

    公开(公告)号:US08369633B2

    公开(公告)日:2013-02-05

    申请号:US12605255

    申请日:2009-10-23

    CPC classification number: H04N19/33 H04N19/103 H04N19/136 H04N19/17

    Abstract: Techniques pertaining to scalable video codec are disclosed. According to one aspect of the present invention, a video image is analyzed and a region of interest (ROI) and a region of non-interest (non-ROI) are identified. By comparing the non-ROI image with that of a previous image, a background ignored identifier is created indicating whether the non-ROI can be ignored during encoding and decoding processes. Based on the status of the background ignored identifier, the encoder encodes the images into a basic layer (BL) and an enhanced layer (EL), and transmits the coded bit streams along with the identifier to a decoder. The decoder reconstructs the image based on the identifier and the BL and the EL bit streams.

    Abstract translation: 公开了与可伸缩视频编解码器有关的技术。 根据本发明的一个方面,分析视频图像,并且识别感兴趣区域(ROI)和非感兴趣区域(非ROI)。 通过将非ROI图像与先前图像的非ROI图像进行比较,创建背景忽略的标识符,指示在编码和解码过程期间是否可以忽略非ROI。 基于背景忽略标识符的状态,编码器将图像编码为基本层(BL)和增强层(EL),并将编码的比特流与标识符一起发送到解码器。 解码器基于标识符和BL和EL比特流重构图像。

    Degenerative inductor-based gain equalization
    9.
    发明授权
    Degenerative inductor-based gain equalization 有权
    退化电感式增益均衡

    公开(公告)号:US06933782B1

    公开(公告)日:2005-08-23

    申请号:US10956966

    申请日:2004-10-01

    Applicant: Jinghui Lu

    Inventor: Jinghui Lu

    CPC classification number: H03M9/00 H03L7/06

    Abstract: Described are high-speed parallel-to-serial converters. The converters include data combiners with differential current-steering circuits that respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment includes inductive and resistive loads to equalize the gain over the frequency of interest to reduce data-deterministic jitter.

    Abstract translation: 描述了高速并行到串行转换器。 转换器包括具有差分电流 - 转向电路的数据组合器,其通过产生表示并行数据位的差分串行版本的互补电流信号来响应并行数据位。 一个实施例包括电感和电阻负载以均衡感兴趣频率上的增益以减少数据确定性抖动。

    Frequency multiplier and amplification circuit
    10.
    发明授权
    Frequency multiplier and amplification circuit 有权
    倍频器和放大电路

    公开(公告)号:US06864728B1

    公开(公告)日:2005-03-08

    申请号:US10377948

    申请日:2003-02-28

    Applicant: Jinghui Lu

    Inventor: Jinghui Lu

    Abstract: A frequency multiplier and amplification circuit are disclosed. One embodiment of the present invention comprises: a multiplier operably coupled to multiply a first sinusoidal waveform having a first frequency with a second sinusoidal waveform having a second frequency to produce a third sinusoidal waveform, having a frequency representative of a difference between the first frequency and the second frequency, and a fourth sinusoidal waveform having a frequency representative of a sum of the first and second frequencies; and a frequency-tuned load operably coupled to substantially attenuate the third sinusoidal waveform and to substantially pass the fourth sinusoidal waveform as an output of the frequency-tuned multiplier circuit. The frequency-tuned multiplier circuit can be a single-ended multiplier circuit or a differential multiplier circuit with corresponding single-ended or differential first and second sinusoidal waveforms.

    Abstract translation: 公开了一种倍频器和放大电路。 本发明的一个实施例包括:乘法器,可操作地耦合以将具有第一频率的第一正弦波形与具有第二频率的第二正弦波形相乘以产生第三正弦波形,其具有代表第一频率和 第二频率和具有表示第一和第二频率之和的频率的第四正弦波形; 以及频率调谐负载,其可操作地耦合以基本上衰减所述第三正弦波形并且基本上将所述第四正弦波形作为所述频率调谐乘法器电路的输出。 频率调谐乘法器电路可以是具有对应的单端或差分第一和第二正弦波形的单端乘法器电路或差分乘法器电路。

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