公开(公告)号：US08233477B1

公开(公告)日：2012-07-31

申请号：US12079026

申请日：2008-03-24

申请人： Joel R. Goergen ,  John D'Ambrosia

发明人： Joel R. Goergen ,  John D'Ambrosia

IPC分类号： H04L12/50

CPC分类号： H04L49/40 ,  H04L49/101

摘要： Methods of operating a packet network device having multiple serial channels crossing a backplane are disclosed. In at least one embodiment, a management function performs dynamic modifications to the packet network device configuration in response to detected backplane errors. These modifications can directly alter a characteristic of a channel that is generating errors, or can indirectly affect such a channel by directly altering a characteristic of an “aggressor” channel that is indicated as producing crosstalk on that channel. Other embodiments are also described and claimed.

摘要翻译： 公开了具有跨越背板的多个串行通道的分组网络设备的操作方法。 在至少一个实施例中，响应于检测到的背板错误，管理功能对分组网络设备配置执行动态修改。 这些修改可以直接改变正在产生错误的信道的特性，或者可以通过直接改变在该信道上产生串扰的“侵略者”信道的特性来间接地影响这样的信道。 还描述和要求保护其他实施例。

公开(公告)号：US07945884B1

公开(公告)日：2011-05-17

申请号：US12080964

申请日：2008-04-08

申请人： Joel R. Goergen ,  John D'Ambrosia

发明人： Joel R. Goergen ,  John D'Ambrosia

IPC分类号： G06F17/50

CPC分类号： G06F13/409

摘要： Methods of designing a backplane, a backplane, and a packet switch using such a backplane are disclosed. The backplane comprises communication channels that connect each of a set of first card slots to each of a set of second card slots. Instead of forcing the backplane to route the communication channels to match a preset card configuration, the backplane communication channels are routed so as to reduce crosstalk and attenuation on at least the most difficult routing pairs. The cards perform logical translation of their backplane traffic to conform to the physical pin assignment for the particular card slot in which they are inserted. Other embodiments are also described and claimed.

摘要翻译： 公开了使用这种背板设计背板，背板和分组交换机的方法。 背板包括将一组第一卡槽中的每一个连接到一组第二卡槽中的每一个的通信通道。 代替强制背板来路由通信信道以匹配预设的卡配置，背板通信信道被路由以便在至少最困难的路由对上减少串扰和衰减。 这些卡执行其背板流量的逻辑转换以符合其插入的特定卡槽的物理引脚分配。 还描述和要求保护其他实施例。

公开(公告)号：US20050181673A1

公开(公告)日：2005-08-18

申请号：US10779241

申请日：2004-02-13

申请人： John D'Ambrosia ,  Steven Millard ,  Michael Fogg

发明人： John D'Ambrosia ,  Steven Millard ,  Michael Fogg

IPC分类号： H01R12/16 ,  H01R13/514 ,  H01R13/648

CPC分类号： H01R13/6585 ,  H01R13/514 ,  H01R13/6474 ,  H01R13/6477

摘要： A high speed signal connector having a plurality of signal conductors disposed within the housing and a ground bus or plane disposed within the housing and including a plurality of coextensive layers of different conductive materials including at least a first conductive base layer having predetermined conductivity and permeability and a second conductive top layer have predetermined conductivity and permeability. A multiple layer common ground provides for improved current flow within the common ground so as to minimize cross talk between signal contacts. As a result, the present invention provides a connector for high frequency signal transmission which exhibits an attenuation characteristic which is substantially independent of frequency within a predetermined and selectable frequency range and which permits the tailoring of the attenuation and phase response of the connector as a function of frequency.

摘要翻译： 一种高速信号连接器，其具有设置在壳体内的多个信号导体和设置在壳体内的接地母线或平面，并且包括多个不同导电材料的共同延伸层，至少包括具有预定导电性和磁导率的第一导电基底层， 第二导电顶层具有预定的导电性和导磁率。 多层公共地面提供公共地面内改善的电流，从而最小化信号触点之间的串扰。 结果，本发明提供了一种用于高频信号传输的连接器，其具有在预定和可选择的频率范围内基本上与频率无关的衰减特性，并且允许调整连接器的衰减和相位响应作为功能 的频率。

公开(公告)号：US20070236892A1

公开(公告)日：2007-10-11

申请号：US11400561

申请日：2006-04-07

申请人： Steven Millard ,  John D'Ambrosia

发明人： Steven Millard ,  John D'Ambrosia

IPC分类号： H05K7/20

CPC分类号： H05K7/1061 ,  H01L23/467 ,  H01L2924/0002 ,  H01L2924/00

摘要： A heat relief socket is provided where a contact carrier substrate is provided carrying a plurality of contacts, and is supported by a frame. The frame has an open area therethrough which can receive air flow to cool the bottom of a chip carried by the socket and the contacts themselves.

摘要翻译： 提供了一种放热插座，其中设置有承载多个触点的接触载体基板，并且由框架支撑。 框架具有通过其的开放区域，其可以接收空气流以冷却由插座和接触件本身承载的芯片的底部。