公开(公告)号：US08233477B1

公开(公告)日：2012-07-31

申请号：US12079026

申请日：2008-03-24

申请人： Joel R. Goergen ,  John D'Ambrosia

发明人： Joel R. Goergen ,  John D'Ambrosia

IPC分类号： H04L12/50

CPC分类号： H04L49/40 ,  H04L49/101

摘要： Methods of operating a packet network device having multiple serial channels crossing a backplane are disclosed. In at least one embodiment, a management function performs dynamic modifications to the packet network device configuration in response to detected backplane errors. These modifications can directly alter a characteristic of a channel that is generating errors, or can indirectly affect such a channel by directly altering a characteristic of an “aggressor” channel that is indicated as producing crosstalk on that channel. Other embodiments are also described and claimed.

摘要翻译： 公开了具有跨越背板的多个串行通道的分组网络设备的操作方法。 在至少一个实施例中，响应于检测到的背板错误，管理功能对分组网络设备配置执行动态修改。 这些修改可以直接改变正在产生错误的信道的特性，或者可以通过直接改变在该信道上产生串扰的“侵略者”信道的特性来间接地影响这样的信道。 还描述和要求保护其他实施例。

公开(公告)号：US07945884B1

公开(公告)日：2011-05-17

申请号：US12080964

申请日：2008-04-08

申请人： Joel R. Goergen ,  John D'Ambrosia

发明人： Joel R. Goergen ,  John D'Ambrosia

IPC分类号： G06F17/50

CPC分类号： G06F13/409

摘要： Methods of designing a backplane, a backplane, and a packet switch using such a backplane are disclosed. The backplane comprises communication channels that connect each of a set of first card slots to each of a set of second card slots. Instead of forcing the backplane to route the communication channels to match a preset card configuration, the backplane communication channels are routed so as to reduce crosstalk and attenuation on at least the most difficult routing pairs. The cards perform logical translation of their backplane traffic to conform to the physical pin assignment for the particular card slot in which they are inserted. Other embodiments are also described and claimed.

摘要翻译： 公开了使用这种背板设计背板，背板和分组交换机的方法。 背板包括将一组第一卡槽中的每一个连接到一组第二卡槽中的每一个的通信通道。 代替强制背板来路由通信信道以匹配预设的卡配置，背板通信信道被路由以便在至少最困难的路由对上减少串扰和衰减。 这些卡执行其背板流量的逻辑转换以符合其插入的特定卡槽的物理引脚分配。 还描述和要求保护其他实施例。

公开(公告)号：US08304659B2

公开(公告)日：2012-11-06

申请号：US11977783

申请日：2007-10-26

申请人： Joel R. Goergen

发明人： Joel R. Goergen

IPC分类号： H05K1/00

CPC分类号： H05K1/0242 ,  H01P3/081 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/09745 ,  H05K2201/098 ,  Y10T29/49126

摘要： Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.

摘要翻译： 公开了电路板及其制造方法。 电路板使用形成为包括纵向通道的导体承载高速信号。 通道增加了导体的表面积，从而增强了导体承载高速信号的能力。 在至少一些实施例中，通道内的介电常数和通道之外的介质常数之间也存在不连续性，这被认为可减少信号损耗。

公开(公告)号：US08259847B2

公开(公告)日：2012-09-04

申请号：US13272329

申请日：2011-10-13

申请人： Yi Zheng ,  Joel R. Goergen

发明人： Yi Zheng ,  Joel R. Goergen

IPC分类号： H04K1/02 ,  H04L27/00

CPC分类号： H04L25/4917 ,  H04L1/0063 ,  H04L25/4904 ,  H04L25/497

摘要： Methods and apparatus for serial channel operation are disclosed. An N+1-level signaling scheme is used to transmit N staggered but overlapping NRZ sub-sequences concurrently on a serial channel. Each sequence has a bit rate R and an essential bandwidth of R Hz. The combined bit rate of the channel is N×R, but due to a lack of correlation between the sub-sequences, the essential bandwidth remains approximately R Hz. The signaling scheme also contains redundancy that allows some errors to be detected and/or corrected. Other embodiments are also described and claimed.

公开(公告)号：US07336502B1

公开(公告)日：2008-02-26

申请号：US10454735

申请日：2003-06-03

申请人： Joel R. Goergen

发明人： Joel R. Goergen

IPC分类号： H01R12/16

CPC分类号： H05K1/0251 ,  H05K1/0245 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09781

摘要： A high-speed router backplane is disclosed. The router backplane uses differential signal pairs on multiple signal layers, each sandwiched between a pair of digital ground layers. To reduce routing complexity, at least some of the differential signal pairs route through a via pair, somewhere along their path, to a different signal layer. Specific via designs reduce differential signal distortion due to the via pair, allowing the backplane to operate reliably at differential signal rates in excess of 3 Gigabits per second. In particular, each via passes through nonfunctional conductive pads on selected digital ground plane layers, the pads separated from the remainder of its ground plane layer by a clearance, thereby modifying the impedance of the via and reducing reflections from the stubs created by the via.

摘要翻译： 公开了一种高速路由器背板。 路由器背板在多个信号层上使用差分信号对，每个信号对夹在一对数字接地层之间。 为了降低路由复杂度，差分信号对中的至少一些在其路径的某处沿着不同的信号层路由通路对。 特定的通孔设计可减少由于通孔对导致的差分信号失真，从而允许背板在差分信号速率下可靠地运行，每秒超过3千兆位。 特别地，每个通孔通过选定的数字接地平面层上的非功能导电焊盘，焊盘与其接地平面层的其余部分间隔一定距离，从而修改通孔的阻抗并减少由通孔产生的短截线的反射。

公开(公告)号：US07239527B1

公开(公告)日：2007-07-03

申请号：US11009408

申请日：2004-12-08

申请人： Joel R. Goergen

发明人： Joel R. Goergen

IPC分类号： H01R12/16

CPC分类号： H05K1/0237 ,  H05K1/0219 ,  H05K1/0225 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09609 ,  H05K2201/09663

摘要： For electrical backplanes and the like, a power plane adaptation to improve the propagation of high-speed signals through clearances in an embedded power plane is disclosed. In exemplary embodiments, the power plane is segmented in a high-speed connector region, such that a portion of the metal layer that forms the power plane is retained in the high-speed connector region—but isolated from the power-delivery portion of the power plane. The isolated portion is connected to digital ground, and clearances are formed therein where high-speed signaling throughholes will pass through the region. In some embodiments, various attainable advantages include better manufacturability, better matching and control of high-speed signaling throughhole impedance, and improved noise isolation. Other embodiments are described and claimed.

摘要翻译： 对于电气背板等，公开了一种用于改善高速信号通过嵌入式电源平面中的间隙的传播的电力平面适配。 在示例性实施例中，电力平面在高速连接器区域中分段，使得形成电力平面的金属层的一部分保持在高速连接器区域中，但是与电力输送部分 电力飞机 隔离部分连接到数字地，并且在其中形成间隙，其中高速信令通孔将通过该区域。 在一些实施例中，各种可获得的优点包括更好的可制造性，更好地匹配和控制高速信号通孔阻抗以及改进的噪声隔离。 描述和要求保护其他实施例。

公开(公告)号：US06941649B2

公开(公告)日：2005-09-13

申请号：US10068745

申请日：2002-02-05

申请人： Joel R. Goergen

发明人： Joel R. Goergen

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H05K3/02

CPC分类号： H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

摘要： The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.

摘要翻译： 所公开的板制造技术和设计特征使得能够构建用于路由器等的可靠的，高层次的和经济的背板，其需要以2.5Gbps或更高的速度跨越背板的大量信令路径，以及 作为路由器组件的大量功率分配。 所公开的技术和特征允许相对较厚（例如，三或四盎司铜）功率分配平面与公共背板中的大量高速信号层组合。 使用传统技术，由于需要的层数和配电层的厚度，这种结构将是不可能的。 所公开的实施例使用新颖的层布置，材料选择，处理技术和面板特征来在单个机械稳定的板中产生期望的高速层和低噪声大功率分配层。

公开(公告)号：US09560774B2

公开(公告)日：2017-01-31

申请号：US13420167

申请日：2012-03-14

申请人： Joel R. Goergen ,  Greg Hunt

发明人： Joel R. Goergen ,  Greg Hunt

IPC分类号： H05K3/20 ,  H05K3/42 ,  H05K1/02 ,  H05K3/00

CPC分类号： H05K3/429 ,  H05K1/0216 ,  H05K1/0237 ,  H05K3/0047 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09845 ,  H05K2203/0207 ,  H05K2203/0242 ,  H05K2203/175 ,  Y10T29/49165

摘要： A high-speed router backplane is disclosed. The router backplane uses differential signal pairs on multiple signal layers, each sandwiched between a pair of digital ground layers. Thru-holes are used to connect the differential signal pairs to external components. To reduce routing complexity, at least some of the differential signal pairs route through a via pair, somewhere along their path, to a different signal layer. At least some of the thru-holes and vias are drilled to reduce an electrically conductive stub length portion of the hole. The drilled portion of a hole includes a transition from a first profile to a second profile to reduce radio frequency reflections from the end of the drilled hole.

摘要翻译： 公开了一种高速路由器背板。 路由器背板在多个信号层上使用差分信号对，每个信号对夹在一对数字接地层之间。 通孔用于将差分信号对连接到外部组件。 为了降低路由复杂度，差分信号对中的至少一些在其路径的某处沿着不同的信号层路由通路对。 钻出至少一些通孔和通孔以减少孔的导电短截线长度部分。 孔的钻孔部分包括从第一轮廓到第二轮廓的转变，以减少从钻孔的端部的射频反射。

公开(公告)号：US08345439B1

公开(公告)日：2013-01-01

申请号：US12313265

申请日：2008-11-18

申请人： Joel R. Goergen ,  Donald Lewis

发明人： Joel R. Goergen ,  Donald Lewis

IPC分类号： H05K1/11

CPC分类号： H04L49/40 ,  H05K7/1458 ,  H05K2201/044

摘要： A modular packet network device has a chassis in which multiple logic cards mate to the front side of an electrical signaling backplane. Logic power for the logic cards is supplied from a group of power converter cards that convert primary power to the logic voltages required by the logic cards. The power converter cards lie in a separate cooling path behind the backplane. Advantages achieved in at least some of the embodiments include removing primary power planes from the signaling backplane or portion of the backplane, providing redundant, upgradeable power modules whose individual failure does not cause logic card failure, and providing cool air to power converter circuits that would be subject to only heated air if located on the logic cards. Other embodiments are also described and claimed.

摘要翻译： 模块化分组网络设备具有其中多个逻辑卡配合到电信令背板的前侧的机箱。 逻辑卡的逻辑电源由一组将主电源转换为逻辑卡所需的逻辑电压的电源转换器卡提供。 电源转换卡位于背板背后的单独冷却路径中。 在至少一些实施例中实现的优点包括从信令背板或背板的一部分移除主电源层，提供冗余的可升级电源模块，其单独的故障不会导致逻辑卡故障，并向功率转换器电路提供冷空气， 如果位于逻辑卡上，只能加热空气。 还描述和要求保护其他实施例。

公开(公告)号：US20120144665A1

公开(公告)日：2012-06-14

申请号：US13400207

申请日：2012-02-20

申请人： Joel R. Goergen ,  Greg Hunt ,  Peter Tomaszewski ,  Joseph Pankow ,  Michael Laudon

发明人： Joel R. Goergen ,  Greg Hunt ,  Peter Tomaszewski ,  Joseph Pankow ,  Michael Laudon

IPC分类号： H05K3/32 ,  H05K3/10 ,  H05K3/30

CPC分类号： H05K1/111 ,  H05K1/0245 ,  H05K2201/0187 ,  H05K2201/0969 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49155 ,  Y10T29/49165

摘要： The characteristic impedance of a surface pad is manipulated by reticulating the pad and filling the spaces with a dielectric material, providing an inductive element in the coupling of the surface pad to an underlying ground pad of a ground plane, or a combination of these approaches. In appropriate embodiments, acceptable signal trace routing paths will exist in an embedded signal layer under the ground plane and crossing under the surface pad. Other embodiments are also described and claimed.

摘要翻译： 表面焊盘的特征阻抗是通过网状网格化和用介电材料填充空间来操作的，在表面焊盘与接地平面的下方接地焊盘的耦合中提供电感元件，或这些方法的组合。 在适当的实施例中，可接受的信号迹线路由路径将存在于地平面下方的嵌入式信号层中，并在表面焊盘下交叉。 还描述和要求保护其他实施例。