公开(公告)号：US06304479B1

公开(公告)日：2001-10-16

申请号：US09602758

申请日：2000-06-23

申请人： Joerg Vollrath ,  Michael Fera ,  Philip Moore

发明人： Joerg Vollrath ,  Michael Fera ,  Philip Moore

IPC分类号： G11C506

CPC分类号： G11C5/063 ,  G11C7/18

摘要： A memory array, in accordance with the invention, includes a plurality of memory cells disposed in an array. A plurality of bitlines are included for reading and writing data to and from the memory cells. The plurality of bitlines include a first group of bitlines and a second group of bitlines. Each bitline of the first group is interposed between bitlines of the second group, and each bitline of the second group is interposed between bitlines of the first group. The first group of bitlines are active when the second group of bitlines are inactive, and the second group of bitlines are active when the first group of bitlines are inactive such that adjacent inactive bitlines provide a shield to prevent cross-coupling between active bitlines.

摘要翻译： 根据本发明的存储器阵列包括以阵列布置的多个存储单元。 包括用于从存储器单元读取和写入数据的多个位线。 多个位线包括第一组位线和第二组位线。 第一组的每个位线插在第二组的位线之间，并且第二组的每个位线插在第一组的位线之间。 当第二组位线不活动时，第一组位线是活动的，并且当第一组位线不活动时第二组位线是活动的，使得相邻的非活动位线提供屏蔽以防止有源位线之间的交叉耦合。