公开(公告)号：US06111913A

公开(公告)日：2000-08-29

申请号：US859544

申请日：1997-05-20

申请人： John Ashley Murdock ,  Agnes Yee Ngai ,  Stephen Philip Pokrinchak

发明人： John Ashley Murdock ,  Agnes Yee Ngai ,  Stephen Philip Pokrinchak

IPC分类号： H04N7/30 ,  H04N7/26 ,  H04N7/50

CPC分类号： H04N19/42 ,  H04N19/126 ,  H04N19/132 ,  H04N19/152 ,  H04N19/159 ,  H04N19/176 ,  H04N19/18 ,  H04N19/61 ,  H04N19/149 ,  H04N19/15 ,  H04N19/70

摘要： An MPEG2 compliant digital video encoder system employs an I-frame video encoder module having a quantization unit and variable length encoding to encode coefficients of each macroblock of a picture. Bit regulation schemes are presented for constraining selected coefficients of a macroblock if the bit rate of two prior macroblocks in a row exceeded a bit rate limit, or if the bit rate of the current nonintra macroblock is greater than a predetermined megabits per second (Mbps) limit. Pattern constraining is implemented within the quantization unit. For nonintra pictures, the conventional variable length coding process is modified to generate a Fixed Coded Block Pattern (FCBP) header for each macroblock of the picture for outputting in the bitstream prior to coding of the coefficients. The FCBP signifies that each block of the macroblock contains at least one nonzero coefficient. The regulation scheme then ensures that each block of the macroblock includes at least one nonzero coefficient by setting one of the coefficients in an all zeros block to a nonzero value.

摘要翻译： MPEG2兼容的数字视频编码器系统采用具有量化单位和可变长度编码的I帧视频编码器模块来编码图像的每个宏块的系数。 如果一行中的两个先前宏块的比特率超过比特率限制，或者如果当前nonintra宏块的比特率大于每秒预定兆比特（Mbps），则给出限制宏块的选定系数的比特调节方案， 限制。 模式约束在量化单元内实现。 对于非暗视频图像，常规可变长度编码处理被修改以在图像的每个宏块之前生成用于在编码系数之前在比特流中输出的固定编码块模式（FCBP）头部。 FCBP表示宏块的每个块包含至少一个非零系数。 调节方案然后通过将全零块中的系数之一设置为非零值来确保宏块的每个块包括至少一个非零系数。

公开(公告)号：US5661524A

公开(公告)日：1997-08-26

申请号：US612639

申请日：1996-03-08

申请人： John Ashley Murdock ,  Agnes Yee Ngai ,  Everett George Vail, III

发明人： John Ashley Murdock ,  Agnes Yee Ngai ,  Everett George Vail, III

IPC分类号： H04N7/32 ,  G06T9/00 ,  H03M7/36 ,  H04N7/26

CPC分类号： H04N19/51 ,  H04N19/56

摘要： Method and apparatus for calculating motion vectors. The method and apparatus calculate a motion trajectory value and initial base weights such that when x is the horizontal offset of the current macroblock from the left edge of the search window, and y is the vertical offset of the current macroblock from the top edge of the search window, and this pair of x and y values are used as the initial base weights, the motion estimation provides the best matched macroblock that has the shortest distance from the current macroblock. When the initial base weights are set to 0's, then the motion estimation will produce the first best matched macroblock encountered by the search circuitry. A scheme is also provided to set the initial base weights so that the best matched macroblock closest to the motion trajectory is selected for the motion estimation.

摘要翻译： 用于计算运动矢量的方法和装置。 所述方法和装置计算运动轨迹值和初始基本权重，使得当x是当前宏块与搜索窗口的左边缘的水平偏移量，并且y是当前宏块距离搜索窗口的左边缘的垂直偏移量 搜索窗口，并且将这对x和y值用作初始基本权重，则运动估计提供与当前宏块具有最短距离的最佳匹配宏块。 当初始基本权重设置为0时，运动估计将产生搜索电路遇到的第一最佳匹配宏块。 还提供了一种设置初始基本权重的方案，使得最接近运动轨迹的最佳匹配宏块被选择用于运动估计。

公开(公告)号：US06301671B1

公开(公告)日：2001-10-09

申请号：US09046287

申请日：1998-03-23

申请人： Charles Edward Boice ,  John Mark Kaczmarczyk ,  John Ashley Murdock ,  Michael Patrick Vachon ,  Robert Leslie Woodard

发明人： Charles Edward Boice ,  John Mark Kaczmarczyk ,  John Ashley Murdock ,  Michael Patrick Vachon ,  Robert Leslie Woodard

IPC分类号： G06F132

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  Y02D10/128

摘要： System for reducing power consumption in MPEG-2 compliant video encoder circuitry employs logic for controlling first clock signals input to functional I, HSU and RSU blocks and functional sub-units performing specific tasks therein. Second clock signals are continuously input to a processing detection circuits requiring continuous clock inputs throughout video encode operations for a functional sub-unit. A trigger signal is asserted by the sub-unit itself or, an external processor, to indicate idle or active processing for that particular sub-unit. The combination of the second clock signals and receipt of the trigger signal enable the sub-unit to generate a sleep signal for that sub-unit which is input to a clock control circuit to either enable input of first clock signals to the functional sub-unit during active processing or, disable input of the first clock signal during idle, in-active processing periods, for as long as the trigger signal is asserted. There are a variety of video input conditions that may be detected which will enable generation of a trigger signal indicating idle processing for one or more functional sub-units, including, for example, detection of still input pictures, fade sequences and specification of high bitstream output rates.

摘要翻译： 用于降低MPEG-2兼容视频编码器电路中的功耗的系统采用逻辑来控制输入到功能I，HSU和RSU块的第一时钟信号以及在其中执行特定任务的功能子单元。 第二时钟信号被连续地输入到在功能子单元的整个视频编码操作中需要连续时钟输入的处理检测电路。 触发信号由子单元本身或外部处理器确定，以指示该特定子单元的空闲或主动处理。 第二时钟信号的组合和触发信号的接收使得子单元能够为输入到时钟控制电路的子单元产生睡眠信号，以使第一时钟信号能够输入到功能子单元 在活动处理期间，或者只要触发信号被断言，则在空闲期间禁用第一时钟信号的输入。 存在可以检测到的各种视频输入条件，其将能够产生指示一个或多个功能子单元的空闲处理的触发信号，包括例如静止输入图像的检测，高比特流的衰落序列和指定 产出率。