公开(公告)号：US06301671B1

公开(公告)日：2001-10-09

申请号：US09046287

申请日：1998-03-23

申请人： Charles Edward Boice ,  John Mark Kaczmarczyk ,  John Ashley Murdock ,  Michael Patrick Vachon ,  Robert Leslie Woodard

发明人： Charles Edward Boice ,  John Mark Kaczmarczyk ,  John Ashley Murdock ,  Michael Patrick Vachon ,  Robert Leslie Woodard

IPC分类号： G06F132

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  Y02D10/128

摘要： System for reducing power consumption in MPEG-2 compliant video encoder circuitry employs logic for controlling first clock signals input to functional I, HSU and RSU blocks and functional sub-units performing specific tasks therein. Second clock signals are continuously input to a processing detection circuits requiring continuous clock inputs throughout video encode operations for a functional sub-unit. A trigger signal is asserted by the sub-unit itself or, an external processor, to indicate idle or active processing for that particular sub-unit. The combination of the second clock signals and receipt of the trigger signal enable the sub-unit to generate a sleep signal for that sub-unit which is input to a clock control circuit to either enable input of first clock signals to the functional sub-unit during active processing or, disable input of the first clock signal during idle, in-active processing periods, for as long as the trigger signal is asserted. There are a variety of video input conditions that may be detected which will enable generation of a trigger signal indicating idle processing for one or more functional sub-units, including, for example, detection of still input pictures, fade sequences and specification of high bitstream output rates.

摘要翻译： 用于降低MPEG-2兼容视频编码器电路中的功耗的系统采用逻辑来控制输入到功能I，HSU和RSU块的第一时钟信号以及在其中执行特定任务的功能子单元。 第二时钟信号被连续地输入到在功能子单元的整个视频编码操作中需要连续时钟输入的处理检测电路。 触发信号由子单元本身或外部处理器确定，以指示该特定子单元的空闲或主动处理。 第二时钟信号的组合和触发信号的接收使得子单元能够为输入到时钟控制电路的子单元产生睡眠信号，以使第一时钟信号能够输入到功能子单元 在活动处理期间，或者只要触发信号被断言，则在空闲期间禁用第一时钟信号的输入。 存在可以检测到的各种视频输入条件，其将能够产生指示一个或多个功能子单元的空闲处理的触发信号，包括例如静止输入图像的检测，高比特流的衰落序列和指定 产出率。

公开(公告)号：US5644504A

公开(公告)日：1997-07-01

申请号：US411239

申请日：1995-03-27

申请人： Charles Edward Boice ,  John Mark Kaczmarczyk ,  Agnes Yee Ngai ,  Robert Leslie Woodard

发明人： Charles Edward Boice ,  John Mark Kaczmarczyk ,  Agnes Yee Ngai ,  Robert Leslie Woodard

IPC分类号： G06T9/00 ,  H04N7/26 ,  H04N7/30 ,  G06K15/00

CPC分类号： H04N19/182 ,  H04N19/112 ,  H04N19/122 ,  H04N19/14 ,  H04N19/172

摘要： Disclosed is a digital video encoder processor for discrete cosine transform encoding. The discrete cosine transform encoding includes the encoding steps of (1) determining the discrete cosine transform field or frame type, (2) addressing individual pixels as either (i) vertically adjacent pixels on consecutive Odd and Even field lines, or (ii) vertically adjacent pixels on consecutive Odd field lines, then consecutive Even field lines; or (iii) vertically adjacent pixels on consecutive Even field lines, then consecutive Odd field lines. These subtractions may be performed between (i) consecutive lines, (ii) odd lines, or (iii) even lines. The next step is finding the smallest variance of the above subtractions to determine the discrete cosine transform coding type. The subtractions are carried out in a dynamically partitionable processor having a plurality of datapaths. The datapaths are partitionable by the action of running opcode into (i) a single wide datapath, and (ii) a plurality of narrow datapaths for calculating the absolute value of the difference between two pixels, and accumulating the results of the subtraction.

摘要翻译： 公开了一种用于离散余弦变换编码的数字视频编码器处理器。 离散余弦变换编码包括（1）确定离散余弦变换场或帧类型的编码步骤，（2）将各个像素寻址为连续奇数和偶数场线上的（i）垂直相邻像素，或（ii）垂直 连续奇数场线上的相邻像素，然后连续偶数场线; 或（iii）连续偶数场线上的垂直相邻像素，然后连续的奇数场线。 这些减法可以在（i）连续行，（ii）奇数行或（iii）偶数行之间执行。 下一步是找到上述减法的最小方差，以确定离散余弦变换编码类型。 在具有多个数据路径的动态可分割处理器中执行减法。 数据路径可以通过运行操作码的操作来分割为（i）单个宽数据路径，以及（ii）用于计算两个像素之间的差的绝对值并且累加减法结果的多个窄数据路径。

公开(公告)号：US6127851A

公开(公告)日：2000-10-03

申请号：US238090

申请日：1999-01-26

申请人： Charles Edward Boice ,  John Mark Kaczmarczyk ,  Michael Patrick Vachon

发明人： Charles Edward Boice ,  John Mark Kaczmarczyk ,  Michael Patrick Vachon

IPC分类号： H01L23/498 ,  H01L23/50 ,  H01L25/00

CPC分类号： H01L23/49838 ,  H01L23/50 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532

摘要： More than 2 power N external conditions are determined by a circuit package. Connections are made from N inputs to either a first or second contact at either a first or second logic state respectively or to digital outputs. The outputs may be sequentially placed at either the first or second logic state. By recording an indication signal from the inputs an electronic circuit is adapted to determine more than 2 power N conditions.

摘要翻译： 超过2个电源N外部条件由电路封装确定。 连接是从N个输入到第一或第二逻辑状态的第一或第二触点或数字输出。 输出可以顺序地置于第一或第二逻辑状态。 通过从输入记录指示信号，电子电路适于确定多于2个功率N条件。

公开(公告)号：US06999511B1

公开(公告)日：2006-02-14

申请号：US09255892

申请日：1999-02-23

申请人： Charles Edward Boice ,  James David Greenfield ,  John Mark Kaczmarczyk ,  Agnes Yee Ngai ,  Stephen Philip Pokrinchak

发明人： Charles Edward Boice ,  James David Greenfield ,  John Mark Kaczmarczyk ,  Agnes Yee Ngai ,  Stephen Philip Pokrinchak

IPC分类号： H04B1/66

CPC分类号： H04N19/126 ,  H04N19/159 ,  H04N19/174 ,  H04N19/186 ,  H04N19/61

摘要： A digital video encoder is presented adapted for dynamically switching between sets of quantizer matrix tables without pausing encoding of a stream of video data. Two or more sets of quantizer matrix tables are held at the encoder's quantization unit and compressed store interface for dynamically switching between sets of quant matrix tables at a picture boundary of the sequence of video data, i.e., without stopping encoding of the sequence of video data. Further, while one set of matrix tables is being employed to quantize the stream of video data, the encoder can be updating or modifying another set of quantization matrix tables, again without stopping encoding of the sequence of video data.

摘要翻译： 呈现适于在不暂停视频数据流的编码的情况下在量化器矩阵表的集合之间动态切换的数字视频编码器。 在编码器的量化单元和压缩存储接口处保存两组或多组量化器矩阵表，用于在视频数据序列的图像边界处动态切换量化矩阵表的集合，即不停止对视频数据序列的编码 。 此外，当采用一组矩阵表来量化视频数据流时，编码器可以在不停止对视频数据序列的编码的情况下，更新或修改另一组量化矩阵表。

公开(公告)号：US5786856A

公开(公告)日：1998-07-28

申请号：US618659

申请日：1996-03-19

申请人： Barbara Ann Hall ,  John Mark Kaczmarczyk ,  Agnes Yee Ngai ,  Robert Leslie Woodward

发明人： Barbara Ann Hall ,  John Mark Kaczmarczyk ,  Agnes Yee Ngai ,  Robert Leslie Woodward

IPC分类号： H04N7/26 ,  H04N7/50 ,  H04N7/18

CPC分类号： H04N19/182 ,  H04N19/126 ,  H04N19/14 ,  H04N19/176 ,  H04N19/61 ,  H04N19/124 ,  H04N19/146 ,  H04N19/149 ,  H04N19/15

摘要： A method for spatial compression of a digital video picture to obtain the quantizer step size so as to avoid over "lossy" reconstruction and loss of detail. The first step is dividing the picture into a plurality of macroblocks, for example, 16.times.16 macroblocks, each macroblock having luminance or chrominance pixel blocks, for example four 8.times.8 pixel blocks. This is followed by multiplying each luminance pixel block by a modified frequency ordered Hadamard matrix to yield a first dimension of each luminance pixel block. The first dimension of each pixel block is then multiplied by the inverse of the modified frequency ordered Hadamard matrix to yield a second dimension of each luminance pixel block. The second dimension of the pixel luminance block is then weighted against a weight matrix, and the individual weighted terms are summed for each pixel block. The minimum of the weighted terms is selected. This minimum is used to detect the edge or texture of the macroblock, e.g., for setting the quantizer step size.

摘要翻译： 一种用于数字视频图像的空间压缩以获得量化器步长的方法，以避免“有损”重建和细节丢失。 第一步是将图像划分为多个宏块，例如16×16个宏块，每个宏块具有亮度或色度像素块，例如四个8×8像素块。 随后将每个亮度像素块乘以修改的频率有序Hadamard矩阵，以产生每个亮度像素块的第一维度。 然后将每个像素块的第一维乘以修改频率有序Hadamard矩阵的倒数，以产生每个亮度像素块的第二维度。 然后将像素亮度块的第二维度相对于加权矩阵进行加权，并且对于每个像素块对各个加权项求和。 选择最小加权项。 该最小值用于检测宏块的边缘或纹理，例如用于设置量化器步长。

公开(公告)号：US06549575B1

公开(公告)日：2003-04-15

申请号：US08745584

申请日：1996-11-07

申请人： Adrian Stephen Butter ,  John Mark Kaczmarczyk ,  Agnes Yee Ngai ,  Edward Francis Westermann ,  Robert J. Yagley

发明人： Adrian Stephen Butter ,  John Mark Kaczmarczyk ,  Agnes Yee Ngai ,  Edward Francis Westermann ,  Robert J. Yagley

IPC分类号： H04N732

CPC分类号： H04N19/53

摘要： Temporal compression of a digital video data stream with hierarchically searching in at least one search unit for pixels in a reference picture to find a best match for the current macroblock. This is followed by constructing a motion vector between the current macroblock and the best match macroblock in the reference picture.

摘要翻译： 对在参考图像中的像素的至少一个搜索单元中进行分层搜索的数字视频数据流的时间压缩，以找到当前宏块的最佳匹配。 随后在参考图片中构建当前宏块和最佳匹配宏块之间的运动矢量。

公开(公告)号：US5768537A

公开(公告)日：1998-06-16

申请号：US605559

申请日：1996-02-22

申请人： Adrian Stephen Butter ,  John Mark Kaczmarczyk ,  Agnes Yee Ngai ,  Robert J. Yagley

发明人： Adrian Stephen Butter ,  John Mark Kaczmarczyk ,  Agnes Yee Ngai ,  Robert J. Yagley

IPC分类号： H04N7/32 ,  G06T9/00 ,  H04N5/14 ,  H04N7/26 ,  H04N7/50 ,  H04N11/04 ,  H04N11/20 ,  H04N7/30

CPC分类号： H04N19/423 ,  H04N19/42 ,  H04N19/61 ,  H04N11/044 ,  H04N11/20 ,  H04N5/147

摘要： A scalable architecture MPEG2 compliant digital video encoder system having an I-frame only video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream. For IPB bitstreams the system includes a second processor element with a reference memory interface, motion estimation and compensation capability, inverse quantization, and inverse discrete cosine transformation, and motion compensation means; and at least one third processor element motion estimation. The system can be in the form of a single integrated circuit chip, or a plurality of integrated circuit chips, that is one for each processor, the I-frame video encoder module, the second processor element, and the third processor element. There can be one or more of the third processor units.

摘要翻译： 一种可扩展架构MPEG2兼容数字视频编码器系统，其具有仅具有I帧视频编码器模块，具有离散余弦变换处理器，量化单元，可变长度编码器，FIFO缓冲器和压缩存储接口，用于生成I帧 包含比特流。 对于IPB比特流，该系统包括具有参考存储器接口，运动估计和补偿能力，反量化和反离散余弦变换的第二处理器元件和运动补偿装置; 以及至少一个第三处理器元件运动估计。 该系统可以是单个集成电路芯片或多个集成电路芯片的形式，其为每个处理器，I帧视频编码器模块，第二处理器元件和第三处理器元件之一。 可以有一个或多个第三处理器单元。

公开(公告)号：US5760836A

公开(公告)日：1998-06-02

申请号：US701422

申请日：1996-08-22

申请人： James David Greenfield ,  Barbara Ann Hall ,  John Mark Kaczmarczyk ,  Agnes Yee Ngai

发明人： James David Greenfield ,  Barbara Ann Hall ,  John Mark Kaczmarczyk ,  Agnes Yee Ngai

IPC分类号： G06T9/00 ,  H04N7/26 ,  H04N7/50 ,  H04N7/36

CPC分类号： H04N19/42 ,  H04N19/124 ,  H04N19/152 ,  H04N19/176 ,  H04N19/61 ,  H04N19/146

摘要： Method and apparatus for encoding a digital video image stream in an encoder. The encoding includes spatial compression of still images in the digital video image stream and temporal compression between the still images. The spatial compression is carried out by converting a time domain image of a macroblock to a frequency domain image of the macroblock, taking the discrete cosine transform of the frequency domain image, transforming the discrete cosine transformed macroblock image by a quantization factor, and run length encoding the quantized discrete cosine transformed macroblock image. The temporal compression is carried out by reconstructing the run length encoded, quantized, discrete cosine transformed image of the macroblock, searching for a best match macroblock, and constructing a motion vector between them. This forms a bitstream of runlength encoded, quantized, discrete cosine transformed macroblocks and of motion vectors. This bitstream is passed to and through a FIFO buffer to a transmission medium. The number of run length encoded bits is fed back to the encoder for calculation of the quantization factor, to thereby avoid overrunning the buffer and interrupting the transmission.

摘要翻译： 用于对编码器中的数字视频图像流进行编码的方法和装置。 编码包括数字视频图像流中的静止图像的空间压缩和静止图像之间的时间压缩。 空间压缩通过将宏块的时域图像转换为宏块的频域图像，以频域图像的离散余弦变换为单位，将离散余弦变换的宏块图像变换为量化因子，运行长度 对量化的离散余弦变换宏块图像进行编码。 通过重建宏块的游程长度编码，量化，离散余弦变换图像，搜索最佳匹配宏块，并在它们之间构建运动矢量来执行时间压缩。 这形成游程长度编码，量化，离散余弦变换宏块和运动矢量的比特流。 该比特流被传送到FIFO缓冲器并通过传输介质。 运行长度编码比特的数量被反馈到编码器以计算量化因子，从而避免超越缓冲器并中断传输。