公开(公告)号：US20060136850A1

公开(公告)日：2006-06-22

申请号：US11015114

申请日：2004-12-17

申请人： John Corbeil ,  Daniel Prevedel ,  Robert Davis

发明人： John Corbeil ,  Daniel Prevedel ,  Robert Davis

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5036

摘要： A method and computer program product for parasitic extraction from a previously calculated capacitance solution include steps of: (a) receiving as input a design database for an integrated circuit design; (b) receiving as input a first set of operating conditions and a second set of operating conditions for the integrated circuit design; (c) calculating a first resistance solution and a single capacitance solution from the design database and the first set of operating conditions; (d) performing a parasitic extraction of the first resistance solution and the single capacitance solution to generate a first set of parasitic values; (e) calculating a second resistance solution from the design database and the second set of operating conditions; (f) performing a parasitic extraction of the second resistance solution and the single capacitance solution to generate a second set of parasitic values; and (g) generating as output the first set of parasitic values and the second set of parasitic values.

摘要翻译： 一种用于从先前计算出的电容解决方案进行寄生提取的方法和计算机程序产品包括以下步骤：（a）接收用作集成电路设计的设计数据库作为输入; （b）作为输入接收用于集成电路设计的第一组工作条件和第二组工作条件; （c）从设计数据库和第一组操作条件计算第一电阻解和单电容解; （d）执行所述第一电阻溶液和所述单电容溶液的寄生提取以产生第一组寄生值; （e）从所述设计数据库和所述第二组操作条件计算第二电阻解; （f）执行所述第二电阻溶液和所述单电容溶液的寄生提取以产生第二组寄生值; 和（g）产生第一组寄生值和第二组寄生值作为输出。

公开(公告)号：US20070079269A1

公开(公告)日：2007-04-05

申请号：US11243839

申请日：2005-10-05

申请人： John Corbeil ,  Michael Saunders

发明人： John Corbeil ,  Michael Saunders

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： The present invention provides a method for performing design rule check (DRC) of an integrated circuit. A design layout of the integrated circuit is provided. The integrated circuit includes a complex circuit. A DRC tool is used to compare a portion of the design layout with a reference layout containing an accurate implementation of the complex circuit. The portion of the design layout corresponds to the complex circuit.

摘要翻译： 本发明提供一种用于执行集成电路的设计规则检查（DRC）的方法。 提供集成电路的设计布局。 集成电路包括复杂电路。 DRC工具用于将设计布局的一部分与包含复杂电路精确实现的参考布局进行比较。 设计布局的部分对应于复杂电路。